38 matching jobs for “Staff Physical Design Engineer”

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Analog Devices

Staff Physical Design Engineer

Bengaluru, Karnataka, India

Technical Ownership Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or …

Added Nov 3, 2026

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Analog Devices

Staff Physical Design Engineer

CLOSED-India, Bangalore, Aveda Meta

Technical Ownership Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or …

Added Nov 3, 2026

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Analog Devices

Staff Design Engineer

Bengaluru, Karnataka, India

The Aerospace , Defense and Communications (ADC) Business Unit at Analog devices is seeking a Staff Digital Design Engineer . The ADC group is a high-impact, innovation focused engineering team working on …

Added Nov 3, 2026

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Analog Devices

Staff Physical Verification Engineer

Bengaluru, Karnataka, India

- Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs. - …

Added Nov 3, 2026

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Analog Devices

Staff Design verification Engineer

Bengaluru, Karnataka, India

As a Staff Digital Design Engineer, you will lead complex digital design projects and provide technical leadership for …

Added Nov 3, 2026

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Analog Devices

Staff Digital Design Engineer

Bengaluru, Karnataka, India

As a Staff Digital Design Engineer, you will lead complex digital design projects and provide technical leadership for …

Added Nov 3, 2026

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Analog Devices

Staff Design Verification Engineer

Bengaluru, Karnataka, India 3 postings

As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing …

Added Nov 3, 2026

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Analog Devices

Staff Design Verification Engineer

CLOSED-India, Bangalore, Aveda Meta

As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing …

Added Nov 3, 2026

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Analog Devices

Staff Design Evaluation Engineer

Bengaluru, Karnataka, India

Design and develop innovative, reliable, and efficient bench hardware and software solutions for complex digital …

Added Nov 3, 2026

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Analog Devices

Staff Design Verification Engineer

Bengaluru, Karnataka, India

Key member of design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible …

Added Nov 3, 2026

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Analog Devices

Staff Engineer, Analog Design

Bengaluru, Karnataka, India

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and …

Added Nov 3, 2026

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Analog Devices

Staff Analog Design Engineer (AMS)

Wilmington, Massachusetts, United States

Pay posted by employer$131,285–$190,108

Added Nov 3, 2026

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Analog Devices

Staff Engineer, Analog Design Engineering

Durham, North Carolina, United States

As a Staff Analog Design Engineer at Analog Devices, you will lead the design and development of complex analog and …

Added Nov 3, 2026

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Analog Devices

Staff Engineer, Digital Design Engineering

Bengaluru, Karnataka, India

Added Nov 3, 2026

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Analog Devices

Staff Engineer, Digital Design Engineering

China, Beijing, Haidian, Xixiaokou

… definition, RTL development, synthesis, timing closure, DFT collaboration, and close partnership with physical design teams to deliver robust, production‑ready designs. Key Responsibilities: Define and develop …

Added Nov 3, 2026

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Analog Devices

Staff Engineer, Design Verification Engineering

Chandler, Arizona, United States

Pay posted by employer$172,390–$199,229 per year

Added Nov 3, 2026

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Analog Devices

Staff Analog & Mixed-Signal Design Engineer - Power/ATE

Wilmington, Massachusetts, United States

Pay posted by employer$131,285–$190,108

involves analysis, research, design, simulation, characterization, and release-to-production of high-performance, power-delivery & measurement …

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Analog Devices

Staff STA Engineer

Bengaluru, Karnataka, India

As a Staff Digital Design Engineer, you will lead complex digital design projects and provide technical leadership for …

Added Nov 3, 2026

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Analog Devices

Staff DFT Engineer

Bengaluru, Karnataka, India

… LBIST, MBIST, boundary scan, and test access strategies Drive testability requirements early in the RTL design phase Balance coverage, test time, power, area, and schedule tradeoffs DFT Implementation (End-to-End …

Added Nov 3, 2026

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Analog Devices

Power IC Design Engineer

Pudong, Shanghai, China

As a Staff Power IC Design Engineer in ADI's Shanghai design center, you will develop high-performance power …

Added Nov 3, 2026

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Analog Devices

Staff Physical Design Engineer

Bengaluru, Karnataka, India

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Required Qualifications · employer excerpt

Strong experience in physical design implementation for complex digital SoCs, typically 8–12+ years in physical design or equivalent level of mastery.
Proven hands-on expertise with industry-standard PNR and signoff tools (e.g., Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus, etc.).
Demonstrated success in closing challenging blocks/subsystems on advanced nodes (timing-, IR-, and congestion-critical designs).

About this opportunity

Original employer description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

Role Overview

The Staff Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery.

Key Responsibilities

Technical Ownership

Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).

Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.

Define and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.

Perform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.

Methodology and Automation

Develop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation).

Proactively identify opportunities for flow improvements and standardization to reduce turnaround time and error rates.

Evaluate EDA tool features and drive best practices in collaboration with CAD/enablement teams.

Technical Leadership & Team Enablement

Provide technical direction to a small group of physical design engineers, including task breakdown, priority setting, and quality expectations.

Mentor junior engineers and NCGs in PNR, STA and debug practices to build a strong second tier of technical capability.

Review floorplans, constraints, and implementation choices from team members, giving clear, actionable feedback.

Act as a go-to technical reference within the PD team.

Cross-Functional Collaboration

Work closely with RTL design, STA, DFT, CAD, and packaging teams to converge on implementation-friendly architectures and constraints.

Communicate risks, options, and trade-offs clearly to project leads and managers, and help shape mitigation plans.

Participate in design reviews and signoff reviews, representing physical design status, risks, and recommendations.

Required Qualifications

Strong experience in physical design implementation for complex digital SoCs, typically 8–12+ years in physical design or equivalent level of mastery.

Proven hands-on expertise with industry-standard PNR and signoff tools (e.g., Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus, etc.).

Demonstrated success in closing challenging blocks/subsystems on advanced nodes (timing-, IR-, and congestion-critical designs).

Solid understanding of:

Floorplanning and partitioning strategies

Power grid and PDN methodology (including IR/EM mitigation)

Advanced clock tree/clock mesh design and constraints

STA constraints (modes/corners, exceptions, derates)

Physical verification and reliability checks

Leadership Expectations

Strong problem-solving and debugging mindset, with a bias toward scalable, automated solutions.

Clear, concise communication skills—able to explain complex technical issues and options to different audiences.

Demonstrated commitment to mentoring, knowledge sharing, and raising the capability of the broader team.

Comfortable operating in a dynamic environment with shifting priorities while maintaining quality and accountability.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

Why this result? · Employer labels

Exact title match

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.