35 matching jobs in Irvine, California, United States

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Broadcom

Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization

Austin, Texas, United States +2 locations

Full time
Regular

Pay posted by employer$150,800–$241,200 USD per year

Added Oct 15, 2026

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Broadcom

ASIC Design Verification Engineer

Irvine, California, United States +2 locations

Full time
Regular

Added Oct 15, 2026

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Broadcom

ASIC Design Engineer

Irvine, California, United States +1 location

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

Added Oct 13, 2026

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Broadcom

Spice Modeling Engineer

Irvine, California, United States

Full time
Regular

Pay posted by employer$129,400–$207,000 USD per year

Added Oct 8, 2026

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Broadcom

Engineering Program Manager

Duluth, Georgia, United States +2 locations

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

Added Oct 7, 2026

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Broadcom

Analog Layout Designer

Irvine, California, United States

Full time
Regular

Pay posted by employer$108,000–$172,800 per year

Added Oct 5, 2026

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Broadcom

Hardware Engineer

Irvine, California, United States

Full time
Regular

Pay posted by employer$108,000–$172,800 per year

Added Oct 5, 2026

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Broadcom

ATE Test Development Engineer

Irvine, California, United States +1 location

Full time
Regular

Pay posted by employer$108,000–$192,000 per year

Added Oct 5, 2026

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Broadcom

Staff Program Manager - Advanced Packaging Technology

Irvine, California, United States

Full time
Regular

Pay posted by employer$109,700–$175,500 per year

Added Oct 5, 2026

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Broadcom

ASIC Design Verification Engineer

Irvine, California, United States +2 locations

Full time
Regular

Pay posted by employer$129,400–$207,000 per year

Added Oct 5, 2026

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Broadcom

Senior Custom ASIC Engineering Lead

San Jose, California, United States +2 locations

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

Added Oct 5, 2026

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Broadcom

Senior Custom ASIC Engineering Lead

San Jose, California, United States +2 locations

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

Added Oct 5, 2026

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Broadcom

Analog & RF IC Senior Layout Engineer

Irvine, California, United States +1 location

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

Added Oct 5, 2026

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Broadcom

Analog/Mixed Signal Verilog Modeling Design Engineer

Irvine, California, United States +1 location

Full time
Regular

Added Oct 5, 2026

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Broadcom

ATE Test Development Engineer

Irvine, California, United States +1 location

Full time
Regular

Pay posted by employer$101,000–$162,000 USD per year

Added Oct 5, 2026

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Broadcom

Design Verification Engineer

Broomfield, Colorado, United States +4 locations

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Added Oct 5, 2026

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Broadcom

product application engineer

Irvine, California, United States +1 location

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Added Oct 5, 2026

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Broadcom

Senior Serdes System Design Engineer/Architect

Austin, Texas, United States +2 locations

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Added Oct 5, 2026

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Broadcom

Mfg Technician Proc/Prod

Irvine, California, United States

Full time
Regular

Pay posted by employer$24.00–$30.00 USD per hour

Added Oct 5, 2026

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Broadcom

Analog and Mixed Signal Design Engineer

Chandler, Arizona, United States +1 location

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

Added Oct 5, 2026

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Broadcom

Senior Serdes System Design Engineer/Architect

Austin, Texas, United States +2 more

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

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About this opportunity

Original employer description

Please Note:

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Job Description:

This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high-speed Serdes at speeds of 100G+.
The types of algorithms that will be implemented include PAM & other higher-order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-idealities.
You will be collaborating closely with analog & digital designers to successfully implement the algorithms in advanced silicon technology nodes and work with DVT/lab engineers to validate your designs for high-volume production.
You will support the group contribute to the development of next-generation wireline communications standards at standard bodies such as IEEE and OIF.

Responsibilities include:

Develop channel models and run simulations to help define Serdes architecture
Define and document signal processing block requirements, architecture, and lab test plan
Develop bit-exact MATLAB and C/C++ system models for simulation and verification
Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs
Work with the design team to perform vector matching verification with RTL simulations
Develop, test, and debug firmware associated with physical layer functionality
Lab testing and debug of Serdes
Documentation/application note development and customer support
Support marketing group with customer meetings and collateral

Job Requirements

B.S.E.E. plus 12+ years relevant experience OR M.S.E.E. plus 10 years required)
Expert knowledge in Communication Theory
Expert knowledge in Digital Signal Processing algorithms
Working knowledge of Analog circuit behavior
Working knowledge of Transmission line theory and s-parameter
Expert in MATLAB, C/C++ programming
Good hands-on skills in the lab
Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.
Experience in equalization techniques for wireline communication applications such as read-channel is also a very big plus.
RTL coding is a plus
Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards is a plus

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Why this result? · Employer labels

Full time
R&D
Regular

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.