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Broomfield, Colorado, United States +4 locations
Pay posted by employer$143,800–$230,000 USD per year
Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 per year
… individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements. The engineer …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 per year
… individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements. The engineer …
San Jose, California, United States
… individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements. Responsibilities …
San Jose, California, United States
Pay posted by employer$120,000–$192,000 per year
… and protocols. The successful candidate will be responsible for various key tasks in the areas of verification of cutting edge network switch routing designs. The daytoday tasks for this position include but are not …
Irvine, California, United States +2 locations
Pay posted by employer$129,400–$207,000 per year
… critically important power efficiency. We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a …
Irvine, California, United States +2 locations
… critically important power efficiency. We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a …
San Jose, California, United States +1 location
Pay posted by employer$101,000–$162,000 USD per year
The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs. Responsibilities include: Operate with a high degree of autonomy, …
San Jose, California, United States +1 location
Pay posted by employer$121,900–$195,000 USD per year
… to low power and most advanced wireless solutions as examples. Responsibilities Develop and execute verification plans for IP blocks at both block and system levels Build and maintain System Verilog /UVM-based …
Irvine, California, United States
ASIC Verification Engineer High Speed Interconnect Product (HSIP) Group The Opportunity Broadcom is the global leader in …
San Jose, California, United States 2 postings
Pay posted by employer$143,800–$230,000 USD per year
Job duties include: Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these …
Irvine, California, United States +1 location
Pay posted by employer$101,000–$162,000 USD per year
… Here you will utilize the technical skills you already learned at school and develop new skills in the verification of communication ASICs with leading edge technologies and tools. You will work closely with marketing, …
USA-Mendota Heights-Northland
Pay posted by employer$109,700–$175,500 USD per year
Senior Digital / Mixed-Signal IC Design or Verification Engineer Location: Mendota Heights, MN or Broomfield, CO Job Description Summary Join …
Bengaluru, India
Job Description: · Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. · Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for …
Bengaluru, India
… for these features. · Architect and develop scalable and re-usable test benches, using the framework of the verification methodology · Build pseudo-random tests to verify and get full Functional coverage · Debug Regression …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 USD per year
Responsibilities: Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these …
Bengaluru, India
… team working on defining many Firsts for the AI Network Infrastructure Ecosystem. - Develop and maintain verification Environment in Mix of SV/UVM. - Understanding of the End to End spec along with Network & System topology. …
San Jose, California, United States 2 postings
Pay posted by employer$121,900–$195,000 USD per year
… for these features. Architect and develop scalable and re-usable test benches, using the framework of the verification methodology Build pseudo-random tests to verify and get full Functional coverage Debug Regression failures, …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 USD per year
Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — …
Fort Collins, Colorado, United States
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
