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Chandler, Arizona, United States
Pay posted by employer$109,700–$175,500 USD per year
Role Overview Broadcom’s Central Engineering Group is seeking an I/O Design Engineer with experience in analog and mixed-signal IC design. The candidate will contribute to the design …
Bengaluru, India
… Virtuoso Layout, Layout XL, VXL, EXL, and Cadence Schematic Capture. Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes. Extensive …
Bengaluru, India
… effectively with the SOC and library teams. Skill Set(Memory): - Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration). - Experience with Cadence Layout …
Bengaluru, India
… communicate effectively with the SOC/library team. Skill Set (Memory): - Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes. - Experience with …
Fort Collins, Colorado, United States +1 location
Pay posted by employer$121,900–$195,000 USD per year
… SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization, clock domain crossing (CDC) analysis and Reset Domain crossing (RDC). Beyond technical …
San Jose, California, United States +1 location
Pay posted by employer$101,000–$162,000 USD per year
The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs. Responsibilities include: Operate with a high degree of autonomy, …
USA-Mendota Heights-Northland
Pay posted by employer$109,700–$175,500 USD per year
Staff Memory Circuit Design Engineer We are looking for energetic and passionate memory design engineers to join our Central …
San Jose, California, United States
Pay posted by employer$120,000–$192,000 per year
… network switches for enterprise and mega scale data centers . We are looking for experienced engineers to design cutting edge CoWos 2.5D , 3D interposer designs. You will be working on designing interposers starting …
Bengaluru, India
We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the …
USA-Mendota Heights-Northland +2 locations
Pay posted by employer$109,700–$175,500 USD per year
… individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art SoC development to meet customer requirements for AI and storage …
Irvine, California, United States +1 location
Pay posted by employer$121,900–$195,000 USD per year
This position is responsible for, but not limited to, the following job duties: Work as part of a physical design team implementing chips from netlist to GDSii with a good understanding of the technology elements …
Bengaluru, India
Analyze different memory architectures and highlight the tradeoffs Design and build memory or circuit blocks at the gate or transistor level Simulate and analyze the circuit design …
Austin, Texas, United States +2 locations
Pay posted by employer$143,800–$230,000 USD per year
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will …
Austin, Texas, United States +2 locations
Pay posted by employer$121,900–$195,000 USD per year
This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will …
San Jose, California, United States +1 location 2 postings
Pay posted by employer$121,900–$195,000 USD per year
You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to …
Fort Collins, Colorado, United States
Pay posted by employer$109,700–$175,500 USD per year
Responsibilities include: Design analog blocks, systems or sub-systems using a combination of behavioral modeling tools and transistor-level …
Bengaluru, India
… of Mixed Signal and IO Library Development team in Central Engineering. Primary responsibilities include: Design and verification of IO interfaces and mixed signal blocks such as POR, process monitors, …
Irvine, California, United States +1 location
Description Join Broadcom's Physical Layer Products (PLP) group, a world-class team responsible for designing and supporting some of the coolest …
Yishun New Town, Singapore
… nodes. Responsibilities: -This individual will be hands-on, heavily involved in day-to-day support of design/layout issues and develop, maintain, and support utilities to improve productivity. - Hands-on, daily …
San Jose, California, United States
Pay posted by employer$121,900–$195,000 USD per year
Broadcom’s Core Switching Group division is seeking a candidate for a DFT engineer. Products include networking switches for Scale up and Scale Out for traditional and AI data centers. This …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
