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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
Armenia
… degree in Electrical Engineering, Computer Science, or a related field. 5+ years of hands-on experience in ASIC design and physical implementation. Proven track record in ASIC physical design and verification preferably …
Tel Aviv, Israel +1 location
… implementation feasibility. Support Hardware & Software Integration: Collaborate closely with digital ASIC design, firmware, and systems engineering teams to ensure accurate fixed-point translation and RTL …
San Jose, California, United States
Pay posted by employer$167,700–$245,200
… more, and work quickly. Join us to power the future of the digital world. Your Impact Participate in the ASIC design verification for Cisco high-end switching products. Perform end-to-end verification of design blocks …
San Jose, California, United States
Pay posted by employer$155,000–$222,600
… experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center …
San Jose, California, United States
Pay posted by employer$167,700–$245,200
… the future of the digital world. Your Impact: You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep …
Bengaluru, India
… the emulation env, build netlists and use the same to speed up the development cycle and find potential ASIC issues during pre-silicon phase • Work with leading emulation vendors to troubleshoot issues. What You’ll …
San Jose, California, United States
Pay posted by employer$167,700–$245,200
… experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center …
San Jose, California, United States
Pay posted by employer$155,000–$222,600
include: Support DFT implementation for ASIC / SoC blocks and subsystems Implement and validate scan insertion, scan compression, OCC, MBIST, boundary …
San Jose, California, United States
Pay posted by employer$186,900–$267,700
… in the lab. Minimum Qualifications Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of …
San Jose, California, United States
Pay posted by employer$155,000–$222,600
… more, and work quickly. Join us to power the future of the digital world. Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. …
Caesarea, Israel +1 location
Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One …
San Jose, California, United States +1 location
Pay posted by employer$167,700–$245,200
Bengaluru, India
… networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of …
San Jose, California, United States
Pay posted by employer$167,700–$245,200
San Jose, California, United States
Pay posted by employer$167,700–$245,200
… and optical link issues during prototype bring-up and system validation. Partner multi-functionally with ASIC architecture, signal integrity, board design, software/diagnostics, and manufacturing teams from early …
San Jose, California, United States
Pay posted by employer$186,900–$267,700
… us to power the future of the digital world. You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, …
Armenia
… DFT solutions. Develop automation and productivity scripts using Python, PERL or TCL to streamline the ASIC design cycle and improve engineering efficiency. Collaborate with experienced DFT Engineers to learn and …
Armenia
… groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical …
Bengaluru, India
… processors and multi-die packages. • DFT Collaboration: Partner closely with Design for Test (DFT) and ASIC design teams during the pre-silicon phase to define testability requirements, evaluate test coverage, and …
Hsinchu, Taiwan +1 location
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
