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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
US, CA, Santa Clara +1 location
… Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Prior experience with arbiters, scheduling, …
US, CA, Santa Clara +1 location
… adoption by joining NVIDIA's Advanced Technology Group! We are looking for a Full-Chip RTL Integration Engineer to join our dynamic and growing FE-ASIC development team. In this role, you will be responsible for …
Israel, Yokneam
NVIDIA networking IC product engineering team is looking for a talented engineer to join our growing failure analysis team and support various activities of IC failures investigations in …
Taiwan, Hsinchu
… thinking, solution focused and attention to detail Ways to stand out from the crowd: Understanding of DFT insertion techniques including SCAN, ATPG, MBIST and IOBIST Demonstrated experience in project management …
Israel, Yokneam +1 location
… and European regulations, IPC specifications and NRC regulations. What we need to see: B.Sc. in Electronic Engineer degree or equivalent experience. 5+ years of experience in high-speed design. Having a detailed knowledge …
US, CA, Santa Clara +1 location
We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and …
US, CA, Santa Clara
We are now looking for a Senior DFX Software Engineer - Machine Learning. Do you like to think creatively and enjoy solving challenges that …
Israel, Yokneam
We are looking for a creative and independent Pre Silicon modelling Reliability Engineer. NVIDIA Networking unit has continuously reinvented itself over two decades. Our high-speed buses & network …
Israel, Yokneam
… Write, execute and debug FW code Manage Failure Analysis of field and production failures Provide DFT recommendations to the design teams Build expertise on production of network products What we need to see: …
Israel, Yokneam +2 locations
… timing ecos generation. Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages. Responsible for a full timing closer and …
US, MA, Westford
… join the team and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the …
India, Bengaluru
NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem …
US, CA, Santa Clara +1 location
NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world's leading SOCs, CPUs, and GPUs. This position offers you a unique …
US, CA, Santa Clara
… world and there has never been a more exciting time to join our team! The NVIDIA VLSI team is looking for a Senior Cell Modeling and Verification Engineer with strong experience in hardware design and methodologies to help …
India, Bengaluru
… meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential …
India, Bengaluru
… to interact with cross functional teams to build consensus. Experience in synthesis, physical design and DFT is a plus. Experience in RTL Build and Design Automation is a plus. Ways to Stand out from the crowd: Chip …
US, CA, Santa Clara +1 location
… is our life’s work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If you want to challenge …
US, CA, Santa Clara
… meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential …
US, CA, Santa Clara +5 locations
… tools (VCS, Verdi or equivalent) Background in UPF power verification is a plus Experience in netlist and DFT verification is a plus Perl/Python and C/C++ programming language experience desirable Knowledge of ASIC …
US, CA, Santa Clara +1 location
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
