Senior ASIC Design Engineer – Clocks IP
US, CA, Santa Clara +1 location
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …
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US, CA, Santa Clara +1 location
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …
US, OR, Hillsboro +3 locations
We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. …
China, Shanghai
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal …
US, CA, Santa Clara +3 locations
… Come join the team and see how you can make a lasting impact on the world. We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all …
US, CA, Santa Clara +1 location
As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level …
Israel, Yokneam
… product will be EOL (end of life). As part of the effort mentioned above, we are looking for an Electronic Engineer to join the System Design Testing Architecture team and lead Systems HW testability definition for NVIDIA’s …
US, CA, Santa Clara
… on the world. At NVIDIA, we are dedicated to pushing the boundaries of technology and innovation. As a Senior Photonic Mixed Signal Compose Validation Engineer, you will play a crucial role in developing and debugging …
US, CA, Santa Clara
… do their best work. Come join the team and see how you can make a lasting impact on the world. Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional, integral team at NVIDIA. We sit at the crossroads of …
China, Beijing
We are hiring a Senior PCIe Firmware Engineer to join the Chip Design PCIe Firmware team, based in Beijing. You will be the team's …
Israel, Tel Aviv
NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best …
Israel, Tel Aviv +3 locations
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet …
US, CA, Santa Clara
At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality …
Israel, Tel Aviv +1 location
… debug, and the ability to scale best practices across multiple programs. This is a great match for an engineer who wants to combine technical depth with broad project impact. What you’ll be doing: Own physical …
US, MA, Westford +2 locations
… to join us today! Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, RTL, and gate level designs. As a senior software …
India, Bengaluru
NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the …
Israel, Yokneam +1 location
NVIDIA is looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies. As a design engineer …
Israel, Yokneam
… teams with smart people who can join us at the forefront of technological advancement. NVIDIA IC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering …
US, CA, Santa Clara
… This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions …
US, CA, Santa Clara
We are looking for an excellent Senior Firmware Engineer to join the Firmware team. The NVIDIA Firmware team develops groundbreaking networking …
Taiwan, Hsinchu
include defining the chip pad ring, substrate interconnect scheme, and lead the package layout design process. We collaborate with …
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