648 matching jobs for “ASIC Design Engineer”

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Intel

GPU Logic Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

GPU Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation …

Added Oct 27, 2026

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Marvell Technology

Principal Engineer, Physical Design

Hsinchu City

Full time
Regular

… and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure …

Added Nov 3, 2026

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Analog Devices

Senior Digital Design Engineer

Bengaluru, Karnataka, India +1 location

… & Scope, Business Impact). Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis) Execute place-and-route, clock tree synthesis, and timing closure using …

Added Nov 3, 2026

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RTX

Principal FPGA/ASIC Verification Engineer (Onsite)- Active Secret

US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A

… aerospace and defense. We are seeking an experienced and highly motivated Principal Electrical or Computer Engineer to lead the design, implementation, and verification of advanced testbenches for a portfolio of …

Added Oct 27, 2026

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Analog Devices

Senior Digital Design Engineer

United Kingdom, Edinburgh, SC, Freer

… with unmatched technologies that sense, measure, and connect. Analog Devices is seeking a senior digital design engineer for its Data Center & Energy (DCE) group in Limerick, Ireland. Within DCE, we deliver …

Added Nov 3, 2026

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Intel

GPU Logic Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

The Role and Impact: As a GPU Logic Design Engineer, you will be instrumental in developing the next generation of graphics IPs, contributing directly …

Added Oct 27, 2026

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Analog Devices

Principal Engineer, Design Verification

United Kingdom, Edinburgh, SC, Freer +2 locations

… phase, through verification planning, implementation, execution, and release of products to customers. The Design Verification Engineer will collaborate with the wider ADI technical community which affords an opportunity …

Added Nov 3, 2026

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Cisco Systems

ASIC STA Technical Lead

San Jose, California, United States

Pay posted by employer$186,900–$267,700

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

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Nvidia

Applied Research Engineer, Chip Design

Santa Clara, California, United States

… of innovation that's fueled by phenomenal technology—and outstanding people! We are seeking a world-class engineer to drive applied research at the intersection of AI and ASIC design. Large language models, coding agents, …

Added Oct 31, 2026

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Cisco Systems

Senior Physical Design Engineer

Caesarea, Israel +1 location

Cisco Silicon One is seeking a Physical Design Technical Leader. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire …

Added Oct 27, 2026

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Cisco Systems

IC Package Design Engineer

San Jose, California, United States

Pay posted by employer$155,000–$222,600

• Contribute to package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed …

Added Oct 27, 2026

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Broadcom

Senior Custom ASIC Engineering Lead

San Jose, California, United States +2 locations

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, …

Added Oct 5, 2026

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Broadcom

Senior Custom ASIC Engineering Lead

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, …

Added Oct 5, 2026

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Intel

Quantum Qubit Design Engineer

Hillsboro, Oregon, United States +7 locations

Full time
Regular

Pay posted by employer$141,910–$269,100 USD per year

… approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum …

Added Oct 27, 2026

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Nvidia

Senior Chip Design Verification Engineer

Beersheba, Southern District, Israel +1 location

NVIDIA is looking for best-in-class Chip Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high …

Added Oct 27, 2026

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RTX

Senior FPGA Design Engineer

Tucson, Arizona, United States

… a safer, more secure world. Join us and help shape the future of aerospace and defense. As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, …

Added Oct 27, 2026

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RTX

Senior FPGA Design Engineer

Tewksbury, Massachusetts, United States

Added Oct 27, 2026

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RTX

FPGA Design Engineer II

Tucson, Arizona, United States

… threat. Our team solves tough, meaningful problems that create a safer, more secure world. As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device families including: Xilinx, …

Added Oct 27, 2026

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Intel

Senior Design Verification Engineer

Santa Clara, California, United States

Full time
Regular

Pay posted by employer$164,470–$311,890 USD per year

About the Role Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of …

Added Oct 27, 2026

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Boeing

ASIC/FPGA Verification Engineer - (Associate, Experienced, or Lead) - SoCal

USA - El Segundo, CA +1 location

In person
Full time
Regular

Pay posted by employer$85,850–$116,150

Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog. Develop self-checking …

Added Oct 13, 2026

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Analog Devices

Principal Engineer, Design Verification

United Kingdom, Edinburgh, SC, Freer +2 more

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Qualifications · employer excerpt

Bachelor's or master’s degree, in Engineering (Electronic Engineering) or equivalent
Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are essential. Be self-motivated and enthusiastic. Strong level of English speaking and writing.
Customer facing experience as verification lead
Experience in both IP and SoC level verification.
Strong demonstrable knowledge of verification-plan generation, coverage analysis, constrained random techniques, assertion based and formal verification techniques with System Verilog.

5 more in the full description below.

About this opportunity

Original employer description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

Job Description:

The charter of ADI’s CSS team is to lead the market in selected technology domains with highly differentiated sensing and signal processing solutions. Today these technology areas include Capacitive Sensing, Optical Image Stabilization, Power management and Audio that drive growth in our portable and non-portable consumer business. As part of our global operation and expanding business needs, we are now seeking to fill key roles in defining, developing and implementing verification solutions for mixed signal ICs in this key market area. This would span the entire development cycle from concept phase, through verification planning, implementation, execution, and release of products to customers. The Design Verification Engineer will collaborate with the wider ADI technical community which affords an opportunity to work with many business units in ADI with exposure to many technologies and products

Responsibilities

Based in United Kingdom (Newbury, Edinburgh) Or Valencia Spain, this position will be responsible for contributing to:

Verification of complex designs and sub-systems using leading edge verification methodologies
Contribute to and Influence the decisions on methodologies/strategies to be adopted for design verification.
Develop testbench architectures and develop using UVM or Formal based verification approaches.
Define verification-plans, functional coverage, tests and verification methodology for block/chip-level verification. Work with the design team in generating verification-plans and closure metrics.
Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer
Continuous interaction with analog co-sim and firmware team.
Technically mentor and guide junior verification engineers on SoC Verification.
Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team
Lead verification efforts at IP or SoC level, effort estimation, project scheduling and tracking, task assignment, reporting to management or customer.

Qualifications

Bachelor's or master’s degree, in Engineering (Electronic Engineering) or equivalent
Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are essential. Be self-motivated and enthusiastic. Strong level of English speaking and writing.
Customer facing experience as verification lead
Experience in both IP and SoC level verification.
Strong demonstrable knowledge of verification-plan generation, coverage analysis, constrained random techniques, assertion based and formal verification techniques with System Verilog.
Demonstrated experience in verification techniques for one or more of the following DSP/Processor subsystems/Formal verification
Expert in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration.
Excellent debugging and analytical skills.
Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl etc.
10-15 years in ASIC design verification.

Additional Preferred Qualifications

Experience with HW emulation or FPGA prototyping
Low power methodologies , e.g. UPF
Experience in behavioural modelling of analogue circuits
Experience in verifying processor based designs
Knowledge of interface protocols e.g. AHB/APB/AXI/I2C/SPMI

#LI-RW1

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

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