302 matching jobs for “Staff Design Verification Engineer”

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Analog Devices

Staff Design Verification Engineer

Bengaluru, Karnataka, India 3 postings

As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most …

Added Nov 3, 2026

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Analog Devices

Staff Design Verification Engineer

CLOSED-India, Bangalore, Aveda Meta

As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most …

Added Nov 3, 2026

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Analog Devices

Staff Design Verification Engineer

United Kingdom, Edinburgh, SC, Freer

… today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X . Staff Design Verification Engineer The Data Center and Energy team at Analog Devices is seeking STAFF DESIGN VERIFICATION ENGINEER. The …

Added Nov 3, 2026

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Analog Devices

Staff Design Verification Engineer

Bengaluru, Karnataka, India

Key member of design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible …

Added Nov 3, 2026

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Analog Devices

Staff Design verification Engineer

Bengaluru, Karnataka, India

As a Staff Digital Design Engineer, you will lead complex digital design projects and provide technical leadership for …

Added Nov 3, 2026

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Analog Devices

Staff Engineer, Design Verification Engineering

Bengaluru, Karnataka, India

As a Staff Design Verification Engineer at Analog Devices, you will provide technical leadership in developing verification strategies for our most …

Added Nov 3, 2026

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GE Aerospace

Staff Engineer - FPGA Design/Verification

Grand Rapids, Michigan, United States +2 locations

Full time
Regular

Summary GE Aerospace is seeking an experienced Staff Engineer – FPGA Design/Verification to lead the development of custom logic for advanced avionics hardware. …

Added Oct 27, 2026

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Analog Devices

Staff Engineer, Design Verification Engineering

Chandler, Arizona, United States

Pay posted by employer$172,390–$199,229 per year

… Learn more at www.analog.com and on LinkedIn and Twitter (X) . Employer: Analog Devices, Inc. Job Title: Staff Engineer, Design Verification Engineering Job Requisition: 1010.1197.6 / R262387 Job Location: Chandler, …

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Analog Devices

Staff Design Verification Engineer – SoC and eFPGA

Austin, Texas, United States

… with architecture, RTL, firmware, and software teams to understand new features and define comprehensive verification strategies. Develop detailed verification plans covering feature interactions, system-level behavior, and …

Added Nov 3, 2026

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Analog Devices

Staff Physical Verification Engineer

Bengaluru, Karnataka, India

- Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs. - Drive tape-out …

Added Nov 3, 2026

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Broadcom

Staff IC Verification Engineer

Fort Collins, Colorado, United States +1 location

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

… individuals to work in SoC and IP development programs. The candidate will be joining a high-performance design team responsible for state-of-the-art subsystem development to meet customer requirements for AI and …

Added Nov 3, 2026

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Micron Technology

Staff Design Engineer

San Jose, California, United States

Pay posted by employer$145,000–$246,000 per year

… deliver required functionalities Participate in the conception and development of new circuits Define and design composition architecture specifications for new features. Support the creation of schematics and/or RTL …

Added Nov 3, 2026

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Hewlett Packard Enterprise

Design Verification Manager

Sunnyvale, California, United States

Pay posted by employer$174,000–$352,500 USD per year

We are seeking a visionary and technically rigorous Design Verification Manager to lead our world-class silicon verification team. In this pivotal leadership role, …

Added Nov 3, 2026

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Arrow Electronics

Design Verification Engineer (eInfochips Inc)

US-CA-San Jose, California

Full time
Regular

… with C knowledge Regression & Coverage Closure What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to …

Added Oct 27, 2026

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Arrow Electronics

Design Verification Engineer(eInfochips Inc)

US-CA-San Jose, California

Full time
Regular

Pay posted by employer$95,900–$149,600

… CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / …

Added Oct 27, 2026

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Broadcom

Staff Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

… position requires a breadth of disciplines and responsibilities in supporting the Processor based subsystem verification for the ‘ASIC Products Division’ within Broadcom Limited. Responsibilities will include Verification …

Added Oct 5, 2026

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Broadcom

Staff Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, partitioning, placement, …

Added Oct 5, 2026

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Marvell Technology

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Santa Clara, California, United States

Regular

… member of Marvell Central Engineering, you will play a leading role on developing next-generation Agentic design verification workflow and its add-on tools. You will have the opportunity to use your extensive design and …

Added Nov 3, 2026

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Analog Devices

Staff Physical Design Engineer

Bengaluru, Karnataka, India

… 16nm, 7nm, 5nm, 4nm). Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets. Define and refine hierarchical PNR strategies, IO …

Added Nov 3, 2026

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Analog Devices

Staff Physical Design Engineer

CLOSED-India, Bangalore, Aveda Meta

Added Nov 3, 2026

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Analog Devices

Staff Physical Design Engineer

CLOSED-India, Bangalore, Aveda Meta

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Required Qualifications · employer excerpt

Strong experience in physical design implementation for complex digital SoCs, typically 8–12+ years in physical design or equivalent level of mastery.
Proven hands-on expertise with industry-standard PNR and signoff tools (e.g., Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus, etc.).
Demonstrated success in closing challenging blocks/subsystems on advanced nodes (timing-, IR-, and congestion-critical designs).

About this opportunity

Original employer description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

Role Overview

The Staff Physical Design Engineer is role which combines deep hands-on implementation expertise with technical leadership. This role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to achieve high-quality, on-time delivery.

Key Responsibilities

Technical Ownership

Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm).

Drive timing closure, congestion resolution, IR/EM, signal integrity, and physical verification (DRC/LVS/antenna) to meet PPA and quality targets.

Define and refine hierarchical PNR strategies, IO ring/PG structures, and integration guidelines for large SoCs.

Perform in-depth analysis and debug of tool issues, timing failures, and physical design anomalies; propose robust, scalable solutions.

Methodology and Automation

Develop, maintain, and enhance physical design methodologies, scripts, and flows (e.g., for PDN, PG, clock structure, exception handling, signoff automation).

Proactively identify opportunities for flow improvements and standardization to reduce turnaround time and error rates.

Evaluate EDA tool features and drive best practices in collaboration with CAD/enablement teams.

Technical Leadership & Team Enablement

Provide technical direction to a small group of physical design engineers, including task breakdown, priority setting, and quality expectations.

Mentor junior engineers and NCGs in PNR, STA and debug practices to build a strong second tier of technical capability.

Review floorplans, constraints, and implementation choices from team members, giving clear, actionable feedback.

Act as a go-to technical reference within the PD team.

Cross-Functional Collaboration

Work closely with RTL design, STA, DFT, CAD, and packaging teams to converge on implementation-friendly architectures and constraints.

Communicate risks, options, and trade-offs clearly to project leads and managers, and help shape mitigation plans.

Participate in design reviews and signoff reviews, representing physical design status, risks, and recommendations.

Required Qualifications

Strong experience in physical design implementation for complex digital SoCs, typically 8–12+ years in physical design or equivalent level of mastery.

Proven hands-on expertise with industry-standard PNR and signoff tools (e.g., Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus, etc.).

Demonstrated success in closing challenging blocks/subsystems on advanced nodes (timing-, IR-, and congestion-critical designs).

Solid understanding of:

Floorplanning and partitioning strategies

Power grid and PDN methodology (including IR/EM mitigation)

Advanced clock tree/clock mesh design and constraints

STA constraints (modes/corners, exceptions, derates)

Physical verification and reliability checks

Leadership Expectations

Strong problem-solving and debugging mindset, with a bias toward scalable, automated solutions.

Clear, concise communication skills—able to explain complex technical issues and options to different audiences.

Demonstrated commitment to mentoring, knowledge sharing, and raising the capability of the broader team.

Comfortable operating in a dynamic environment with shifting priorities while maintaining quality and accountability.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

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