287 matching jobs for “SoC Design Verification Engineer”

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Analog Devices

Staff Physical Verification Engineer

Bengaluru, Karnataka, India

- Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs. - Drive tape-out …

Added Nov 3, 2026

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Intel

Pre-Silicon Verification Engineer

Hillsboro, Oregon, United States +5 locations

Pay posted by employer$122,440–$172,860 USD per year

… execution and expanding market opportunities through internal product development and external ASIC design services. Guided by a data-driven approach, CEG drives scalable, impactful solutions across Intel's …

Added Oct 27, 2026

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Nvidia

Verification Engineer - GPU Fullchip

Bengaluru, Karnataka, India

… is increasingly known as “the AI computing company.” What you’ll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs. Responsible for …

Added Oct 27, 2026

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Broadcom

Staff IC Verification Engineer

Fort Collins, Colorado, United States +1 location

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The …

Added Nov 3, 2026

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Cisco Systems

Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

Bengaluru, Karnataka, India

… Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design verification background with hands-on experience in System Verilog and UVM methodology with in-depth …

Added Oct 27, 2026

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Intel

SoC FPGA prototyping

Bengaluru, Karnataka, India

The Role and Impact As an Emulation Engineer, you will play a pivotal role in developing, testing, and optimizing emulation and FPGA models to enable …

Added Nov 3, 2026

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Marvell Technology

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Santa Clara, California, United States

Regular

… member of Marvell Central Engineering, you will play a leading role on developing next-generation Agentic design verification workflow and its add-on tools. You will have the opportunity to use your extensive design and …

Added Nov 3, 2026

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Broadcom

Design Engineer

Fort Collins, Colorado, United States

Full time
Regular

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class …

Added Oct 5, 2026

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Intel

Sr Deep Learning Verification Engineer

Leixlip, Leinster, Ireland

The Role and Impact As a Sr Deep Learning Hardware Verification Engineer, you will play a pivotal role in shaping the future of AI hardware by validating and optimizing …

Added Oct 27, 2026

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Nvidia

Senior ASIC Verification Engineer - HSIO

Westford, Massachusetts, United States +1 location

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of the next generation of High Speed I/O …

Added Oct 27, 2026

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Intel

Logic Design Engineer

Malaysia, Penang

Devices Development Group Malaysia (DDG-MYS) Client SoC Team is seeking highly motivated engineering talent to join Intel’s next-generation Client SoC development …

Added Oct 27, 2026

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Intel

Logic Design Engineer

Malaysia, Penang

The Role and Impact : Join Intel as an SoC Logic Design Engineer, where you will play a pivotal role in developing the logic design for Intel's …

Added Nov 3, 2026

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Broadcom

IC Design Engineer

Bengaluru, Karnataka, India 3 postings

Full time
Regular

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous …

Added Oct 5, 2026

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Broadcom

IC Design Engineer

Bengaluru, Karnataka, India 2 postings

Full time
Regular

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous …

Added Oct 5, 2026

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Marvell Technology

Design Engineer Intern

Yokneam

Full time
Internship

… above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Soc Design team is responsible for SoC-level design activities and functionality in Marvell switching SoCs. The …

Added Nov 3, 2026

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Intel

CPU HVM Functional-Test Verification Engineer

Malaysia, Penang

As a CPU HVM Functional-Test Verification Engineer, you will be part of the DFT team focusing on validating DFT for manufacturing functional testing …

Added Nov 3, 2026

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Nvidia

GPU Core Pipeline IP Verification Engineer

Bengaluru, Karnataka, India

NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the …

Added Oct 27, 2026

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Broadcom

Physical Design Engineer

San Jose, California, United States +3 locations

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Responsibilities Include: Work on Design Implementation activities related to place and route and/ or timing closure – floor-planning, partitioning, …

Added Oct 31, 2026

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Arrow Electronics

Physcial Design Engineer

US-CA-San Jose, California +1 location

Full time
Regular

… Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff …

Added Oct 27, 2026

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Nvidia

SRAM Design Engineer

Santa Clara, California, United States

… (DIP) group at NVIDIA develops IP for every chip designed at NVIDIA. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One …

Added Oct 27, 2026

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Analog Devices

Staff Physical Verification Engineer

Bengaluru, Karnataka, India

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Required Qualifications · employer excerpt

- Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field.
- Typically 8-12 years of experience in physical verification for complex ASIC/SoC designs, including several successful production tape-outs as signoff owner.
- Proven experience owning DRC/LVS/PERC signoff for at least one 5 nm (or sub-7 nm) production tape-out in a FinFET process
- Deep hands-on expertise with industry-standard PV tools (e.g., Siemens Calibre, Synopsys IC Validator) for DRC, LVS, ERC, PERC and ANT/ESD checks.
- Hands-on experience with Cadence Virtuoso-PV tool integration( Virtuoso layout to Caliber/ICV for DRC/LVS/PERC)

9 more in the full description below.

About this opportunity

Original employer description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

Role

We are seeking a Staff Physical Verification Engineer to own full-chip signoff for advanced SoC/ASIC designs, with end-to-end responsibility from block-level checks to final tape-out. You will lead methodologies and execution for DRC, LVS, PERC and related reliability checks, working closely with Place-n-route, analog/mixed-signal, timing analysis and CAD teams to ensure first-time-right silicon.

Key Responsibilities

- Own full-chip and block-level physical verification signoff, including DRC, LVS, ERC, PERC and antenna/ESD checks for multiple complex SoCs.

- Drive tape-out readiness: manage PV schedules, track violations, converge to zero/signoff-acceptable errors, and deliver clean GDS.

- Develop, maintain, and optimize PV flows and scripts (e.g., Calibre, ICV) for performance, robustness, and ease of use.

- Define and enhance PERC and reliability rule checks (ESD, EOS, EM-related constraints, point-to-point resistance, high current-density paths) in collaboration with reliability, I/O, and analog teams.

- Own the floorplanning and power grid planning to minimize PV iterations and avoid late-stage violations.

- Own debugging of complex DRC/LVS/PERC violations, including corner-case connectivity, device recognition, FinFET-specific rules - restrictive spacing, coloring, cut-mask and EUV/multi-patterning constraints

- Partner with CAD teams to validate and qualify new technology nodes, rule decks, and fill/DFM flows before project adoption.

- Mentor and guide junior and senior engineers on PV best practices, root-cause analysis methodologies, and signoff criteria.

- Act as primary technical interface to foundry and EDA vendors for PV and reliability issues, waivers, and methodology improvements.

Required Qualifications

- Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field.

- Typically 8-12 years of experience in physical verification for complex ASIC/SoC designs, including several successful production tape-outs as signoff owner.

- Proven experience owning DRC/LVS/PERC signoff for at least one 5 nm (or sub-7 nm) production tape-out in a FinFET process

- Deep hands-on expertise with industry-standard PV tools (e.g., Siemens Calibre, Synopsys IC Validator) for DRC, LVS, ERC, PERC and ANT/ESD checks.

- Hands-on experience with Cadence Virtuoso-PV tool integration( Virtuoso layout to Caliber/ICV for DRC/LVS/PERC)

- Strong experience with advanced process nodes (e.g., 5 nm and below) and associated design-rule and reliability challenges.

- Proven track record in driving full-chip PV signoff in digital-on-top, mixed-signal, or multi-voltage SoCs, including hierarchical flows and IP integration.

- Solid scripting skills in at least one of: Python, Perl, Tcl, or Unix shell, for automation and flow development.

- Experience with PERC-based reliability flows for ESD, EOS, LUP and current-density-based checks, including setup, customization, and signoff criteria definition.

- Familiarity with DFM/DFY checks, density/fill strategies, and pattern-matching-driven rule decks

- Strong understanding of physical design (place & route, timing closure, power integrity) and its interaction with PV signoff.

- Excellent problem-solving, debug, and communication skills, with demonstrated ability to lead cross-functional technical closure.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

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