1,000+ matching jobs for “Engineer, Sr. Process Design”

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Analog Devices

Principal Engineer, Design Verification Engineering

Bengaluru, Karnataka, India

Lead design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible …

Added Nov 3, 2026

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Analog Devices

Principal Engineer, Design Verification Engineering

Bengaluru, Karnataka, India

Lead design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible …

Added Nov 3, 2026

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KLA

Sr. Mechanical Design Engineer - Wafer Chucks & Wafer Positioning Stages

Milpitas, California, United States

Full time
Regular

Pay posted by employer$117,800–$172,800 per year

… advancing business priorities by delivering high-impact work across your area of expertise. As a mechanical design engineer specializing in multi axis motion systems for wafer scanning with nanometers level vibration and …

Added Oct 15, 2026

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Stryker

Senior Process Engineer (m/f/d) New Product Development

Tuttlingen, Baden-Wurttemberg, Germany

As part of our international Advanced Operations team, you will actively shape the process development for innovative products in the field of OR infrastructure, from the first idea to the …

Added Oct 27, 2026

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Nike

Senior Designer, NSW Footwear Product Design

Beaverton, Oregon, United States

… scientists, marketing, testing, sustainability, materials, costing, etc.), collaborating within the design community (industrial designers, materials, color, graphics, computational, etc.), and mentoring other …

Added Oct 27, 2026

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Intel

Intel Foundry Process Development Engineer - Lithography

Hillsboro, Oregon, United States

Full time
Regular

Pay posted by employer$133,800–$255,200 USD per year

This position is in the Logic Technology Development team working in one of the most advanced semiconductor process technologies in the world. You will design, execute, and analyze experiments to develop the process of the …

Added Oct 27, 2026

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Applied Materials

Customer Engineer - Process, Diagnostics, and Control

Lehi, Utah, United States

Pay posted by employer$31–$42.40

… in improving defect inspection performance and yield Work with customers and internal teams to understand process flows and inspection requirements Communicate directly with customers to ensure tool uptime and performance …

Added Oct 27, 2026

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Merck (MSD)

Biologics Process R&D Senior Scientist

Rahway, New Jersey, United States

Pay posted by employer$117,000–$184,200

… and robust scientific methodology, we partner to deliver the next medical breakthrough. Biologics Process Research & Development (BPR&D) within our Research & Development Division is on a mission to rapidly …

Added Oct 16, 2026

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GE Aerospace

Entry Level - FPGA Design/Verification Engineer

Grand Rapids, Michigan, United States

Full time
Regular

Summary Collaborate with a team of hardware and systems engineers to design, verify, and integrate FPGAs for avionics hardware. As an Entry Level FPGA Design/Verification Engineer, …

Added Nov 11, 2026

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Boeing

ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal)

USA - Albuquerque, NM

In person
Full time
Regular

Pay posted by employer$136,850–$185,150

ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal) Company: The Boeing Company Boeing Space, …

Added Oct 15, 2026

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Micron Technology

Staff Engineer – Process Development, Wet, NAND

Fab 10N/X, Singapore

Process Development & Margin Improvement Develop and optimize unit wet processes to meet yield and quality …

Added Nov 3, 2026

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Nvidia

Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

Santa Clara, California, United States +4 locations

… compute environments. Turn recurring integration or qualification difficulties into durable automation and process improvements. Define, publish, and actively use metrics for integration latency, flow health, failure …

Added Oct 27, 2026

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Intel

Senior Technical Lead - CPU Physical Design

Bengaluru, Karnataka, India

Full time
Regular

We are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from floorplanning through signoff. The …

Added Oct 27, 2026

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Boeing

Flight Controls Mechanical Hydraulics Design & Analysis Engineer (Experienced or Senior)

USA - North Charleston, SC

In person
Full time
Regular

Flight Controls Mechanical Hydraulics Design & Analysis Engineer (Experienced or Senior) Company: The Boeing Company Boeing Commercial Airplanes is …

Added Oct 12, 2026

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Boeing

Digital Electronics Circuit & Unit Hardware Design Engineer (Lead or Senior)

USA - El Segundo, CA

Full time
Regular

Pay posted by employer$146,200–$197,800

Digital Electronics Circuit & Unit Hardware Design Engineer (Lead or Senior) Company: The Boeing Company oeing Space, Intelligence & Weapons Systems has an …

Added Oct 16, 2026

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Boeing

Experienced or Senior Digital Circuit Card Assembly (CCA) Design Engineer

USA - Huntsville, AL

In person

Pay posted by employer$112,200–$151,800

Focus on electrical design, simulation, verification, and validation testing of high-speed printed circuit board design and electronic …

Added Oct 12, 2026

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Capital One Financial

Product Design Director - Risk Design

McLean, Virginia, United States +2 locations

Product Design Director - Risk Design At Capital One, we’re building a leading information-based technology company. Still …

Added Oct 27, 2026

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Intel

Sr Director, XSE Design Verification Engineering

Santa Clara, California, United States

Full time
Regular

Pay posted by employer$256,050–$361,480 USD per year

The Role and Impact As a Design Verification Engineering Manager, you will lead a dynamic team of design verification engineers responsible …

Added Oct 31, 2026

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Motorola Solutions

Quality & Process Engineer Summer Internship 2027

Elgin, Illinois, United States

Full time

… a quality standpoint with a goal to drive efficiency gains through quality improvements. Lead quality and process improvement across all facets of the operations. Lead resolution and reduction of all escaping customer …

Added Nov 3, 2026

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Boeing

Struct & Payload Design Engr (Payload Systems Design) (Mid- Level or Senior)

USA - North Charleston, SC

In person
Full time
Regular

Pay posted by employer$103,700–$140,300

… delivery milestones and certification requirements Capture lessons learned from emergent issues and drive design or process changes to prevent recurrence Interface with regulatory authorities (including FAA) as needed …

Added Oct 12, 2026

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Analog Devices

Principal Engineer, Design Verification Engineering

Bengaluru, Karnataka, India

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Requirements · employer excerpt

B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.
Strong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.
Proven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.
Expertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.
Experience in architecting scalable testbench environments and defining robust DV flows and methodologies.

10 more in the full description below.

About this opportunity

Original employer description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

Analog Devices is seeking Digital Design Principal Verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.

About ADI:

Analog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.

About the Role

Lead design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI. The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.

Responsibilities

Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.
Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.
Define and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.
Collaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.
Drive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.
Develop and execute end-to-end system-level use cases for comprehensive functional validation.
Architect and implement scalable UVM-based testbenches, DV flows, and methodologies.
Define and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels.
Work cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.
Apply formal verification techniques for IP and subsystem-level validation.
Lead NoC/interconnect verification and ensure robust data flow across the SoC.
Perform performance verification and system-level analysis across real-world use cases.
Drive innovation in verification strategies to meet aggressive schedules and quality goals.
Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.

Requirements

B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.
Strong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.
Proven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.
Expertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.
Experience in architecting scalable testbench environments and defining robust DV flows and methodologies.
Strong background in power-aware verification (UPF), including power analysis and optimization.
Hands-on experience with formal verification, including flow definition, connectivity, and functional property checking.
Solid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.
Experience in security and safety verification, ensuring compliance with secure design and functional safety requirements.
Familiarity with gate-level simulations with timing annotation (GLS).
Strong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.
Good understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).
Exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.
Excellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.
Strong problem-solving mindset with the ability to quickly learn and adopt new technologies

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

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