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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
Santa Clara, California, United States
We are looking for a talented Senior System Software Engineer to help build NVIDIA Halos, our full-stack safety platform for physical AI: autonomous vehicles, humanoids, …
US-CA-San Jose, California +1 location
What You'll Be Doing: RTL to Physical Design (RTL2PD) stage experience RTL2PD Design Engineer(ASIC) MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing Analysis RTL Synthesis, …
China, Shanghai
… needs through prototyping, use-case analysis, and cost/benefit trade-offs. Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to drive design decisions and debug complex issues. …
Santa Clara, California, United States
… needs through prototyping, use-case analysis, and cost/benefit trade-offs. Partner with architecture, ASIC, board/platform, software/firmware, and marketing teams to drive design decisions and debug complex issues. …
Durham, North Carolina, United States
… can make a lasting impact on the world. We're looking for a talented, motivated Senior Design Verification Engineer to join our GPU memory subsystem team in Durham, NC. Looking to join a dynamic team solving complex …
Petaẖ Tiqva, Central District, Israel
… team's engineers have 10+ years of experience, and we are looking for a highly skilled multidisciplinary engineer with proven experience in Signal Integrity engineering to lead the hardware design of our next division …
Santa Clara, California, United States +2 locations
Pay posted by employer$122,440–$232,190 USD per year
… level and strong programming skills in System Verilog and UVM. Hands on verification experience working on ASIC, CPU or GPU. Test Plan development experience at IP level with coverage closures. Coverage driven …
Santa Clara, California, United States +2 locations
Pay posted by employer$141,910–$232,190 USD per year
… level and strong programming skills in System Verilog and UVM. Hands on verification experience working on ASIC, CPU or GPU. Test Plan development experience at IP level with coverage closures. Coverage driven …
Irvine, California, United States
Pay posted by employer$91,100–$146,000 USD per year
… components and equipment based on analysis of specifications and reliability. Layout/design work in a non-ASIC product environment. Work on complex issues where analysis of situations or data requires an in-depth …
Santa Clara, California, United States
… power models to analyze and reduce power consumption of NVIDIA GPUs. You will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams …
Caesarea, Israel
… validation. Define FPGA specifications, develop and implement RTL designs, and collaborate with Hardware, ASIC, Software, and System engineering teams throughout the product lifecycle. Design and integrate high-speed …
Bengaluru, Karnataka, India
… and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, IO planning and …
Sunnyvale, California, United States
Pay posted by employer$120,500–$243,000 USD per year
Software Engineer 3 Location (Hybrid): Sunnyvale, CA HPE Networking is a leader in AI-driven, next-generation networking …
San Jose, California, United States +1 location
Role Overview As a key member of the Worldwide (WW) ASIC Product Development team, you will collaborate closely with silicon and package design, marketing, NPI, …
Office - USA - CA - Headquarters
… and Synopsys tools, achieving multi-clock timing closure and resource optimization. Prototype & Validate ASIC designs on FPGA platforms, executing lab bring-up, in-system debugging, and hardware validation. …
Bengaluru, Karnataka, India
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
Carlsbad, California, United States +1 location
Pay posted by employer$149,100–$218,100
… and work quickly. Join us to power the future of the digital world. Your Impact As a Senior Analog Layout Engineer on the Silicon One Optics team, you won’t just be drawing polygons—you’ll be architecting the physical …
Bengaluru, Karnataka, India
… stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X . Staff Digital Design Engineer Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
