619 matching jobs for “ASIC Engineer”

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Broadcom

IC Design Engineer

Singapore-Yishun

Full time
Regular

Job Description 1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key …

Added Nov 3, 2026

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Broadcom

Principal Mechanical Engineer

Ottawa March Road

Full time
Regular

Pay posted by employer$114,400–$183,000 CAD per year

As a Principal Mechanical Engineer, you will design, develop, and deliver Mechanical assemblies, including full chassis design for Ultra …

Added Oct 9, 2026

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Broadcom

Principal Hardware Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

As a Principal Hardware Engineer, you will be the technical lead responsible for a design team developing and delivering …

Added Oct 9, 2026

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Broadcom

Principal Physical Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — Physical Design …

Added Oct 25, 2026

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Analog Devices

Principal DFT Engineer

Bengaluru, Karnataka, India

Principal Digital DFT Engineer Role Summary The Principal Digital DFT Engineer is responsible for architecting, implementing, and …

Added Nov 3, 2026

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Cisco Systems

Software Engineer

Milpitas, California, United States

Pay posted by employer$155,000–$222,600

… is expected to close on: 11/26/2026 Meet the team We are seeking an experienced and motivated Software Engineer to join our Service Provider High End Router (Cisco 8000) team within the R&D department, contributing to …

Added Oct 29, 2026

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Broadcom

Design Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$120,000–$192,000 per year

The CSG group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multichip solutions to market over the last decade. The group develops Tomahawk ASICs for Scale-Out …

Added Oct 5, 2026

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Cisco Systems

C++ Software Engineer

Belgrade, Central Serbia, Serbia

… with software development teams on application design and development as well as the Hardware and ASIC design teams across various Cisco locations. Identify bottlenecks and bugs, and devise solutions to these …

Added Oct 27, 2026

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Motorola Solutions

Principal Antenna Engineer

Schaumburg, Illinois, United States

Pay posted by employer$100,100–$160,200 USD

… frequency range, such as atmospheric absorption, high path loss, and tight manufacturing tolerances. Custom ASIC Development: Collaborate with our RF ASIC team on development of beamformer IC’s Customer Technical …

Added Nov 3, 2026

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Nvidia

Senior Chip Design Verification Engineer

Beersheba, Southern District, Israel +1 location

… Engineering/Communication Engineering/Computer Engineering 5+ years of proven experience in RTL Frontend ASIC Verification (Chip Design) High Level of English Ways to stand out from the crowd: Extensive experience in …

Added Oct 27, 2026

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RTX

Principal FPGA Design Engineer

US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A

… architecture and design through production and sustainment. The MPD department is seeking a Principal FPGA Engineer to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions …

Added Oct 27, 2026

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Marvell Technology

Principal Hardware Engineer

Santa Clara, California, United States

Full time
Regular

… data economy, whether deployed at the network core or the edge. What You Can Expect The Principal Hardware Engineer will lead the design of these boards from concept through production, working on custom ASIC solutions …

Added Nov 3, 2026

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Broadcom

Principal Physical Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — Physical Design …

Added Oct 31, 2026

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RTX

Principal FPGA Design Engineer

Tucson, Arizona, United States

… over the world, from the ground to exoatmospheric environments and into space. As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and …

Added Oct 27, 2026

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Cisco Systems

Senior RTL Design Engineer

Armenia

… groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical …

Added Oct 27, 2026

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Cisco Systems

Silicon Validation Engineer

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… more, and work quickly. Join us to power the future of the digital world. Your Impact Develop and maintain ASIC APIs and SDKs in C and C++, delivering clean, scalable updates that support emulation, bring-up, and …

Added Oct 30, 2026

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Broadcom

Package Design Engineer

Singapore-Yishun

Full time
Regular

Broadcom is seeking an experienced package design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave …

Added Oct 5, 2026

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Nvidia

Senior Silicon Power Engineer

Bengaluru, Karnataka, India

… bring-up speed, and ultimately what the product delivers in the field. We are hiring a Senior Silicon Power Engineer to own power-feature productization on a flagship silicon program. This is not a coordination role, and it …

Added Oct 27, 2026

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Nvidia

Verification Engineer - PCIE

Bengaluru, Karnataka, India 3 postings

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s …

Added Oct 27, 2026

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Nvidia

Verification Engineer - PCIE

Bengaluru, Karnataka, India

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s …

Added Oct 27, 2026

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Broadcom

Design Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$120,000–$192,000 per year

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About this opportunity

Original employer description

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Job Description:

The CSG group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multichip solutions to market over the last decade. The group

develops Tomahawk ASICs for Scale-Out and Scale-Up AI Networks. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several hundreds of Terabits/sec. These networking ASIC's support a large number of ports ranging from 10/100Mb/s to 1600Gb/s speeds as well as various line interfaces and protocols.

The successful candidate will be responsible for various key tasks in the areas of verification of cutting edge network switch routing designs. The daytoday tasks for this position include but are not limited to the following:

1) Participating in the verification processes of L2/L3 Network Switching and routing ASICs and various subsystems within these chips

2) Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems.

3) Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains

4) Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment.

5) Executing the verification process to completion pre-silicon using various functional and code coverage metrics as measures of completion

The successful candidate will satisfy the following requirements:

1) MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing. Total engineering minimum experience required is typically a BS degree and 8+

years of experience, an MS degree and 6+ years of experience or a PhD and 3+ years of experience or equivalent.

2) Familiar with Hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python) and Object Oriented Programming (OOP).

3) Exposure to cutting edge verification and validation techniques and methodologies using Object Oriented modular reusable environments in languages such as Systemverilog,

Perl, Python

4) Strong understand and prior experience of end-to-end verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production

5) Excellent verbal and written communication skills.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $120,000 - $192,000

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Keywords also found in description

Full time
R&D
Regular

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.