619 matching jobs for “ASIC Engineer”

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Nvidia

Senior ASIC Design Engineer

Santa Clara, California, United States +1 location

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the …

Added Oct 27, 2026

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Nvidia

Senior ASIC Verification Engineer

Austin, Texas, United States +1 location

NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and implementation of the world’s leading SoC's and GPU's. This …

Added Oct 27, 2026

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Hewlett Packard Enterprise

ASIC Design Verification Engineer

Bengaluru, Karnataka, India

… determine best method for accomplishing work and achieving objectives. What You'll Do Develop and enhance ASIC verification environments using the latest methodologies such as UVM. Architect and build block-level, …

Added Nov 3, 2026

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Nvidia

Senior ASIC Power Engineer

Santa Clara, California, United States +3 locations

We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and …

Added Oct 31, 2026

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Hewlett Packard Enterprise

Senior ASIC Verification Engineer

Sunnyvale, California, United States

Pay posted by employer$158,500–$321,000 USD per year

… limits for learning, achievements, and rewards. Position Summary We are seeking a highly motivated Senior ASIC Verification Engineer to join our networking silicon development team. Key Responsibilities: Own and drive …

Added Nov 3, 2026

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Nvidia

Senior ASIC Verification Engineer

Santa Clara, California, United States +4 locations

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed …

Added Oct 27, 2026

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Nvidia

Senior ASIC Verification Engineer

Austin, Texas, United States

NVIDIA is looking for a Senior ASIC Verification Engineer to help verify our global IP! This position offers an opportunity to impact an array …

Added Oct 27, 2026

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Broadcom

ASIC Implementation Engineer PD

San Jose, California, United States

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves …

Added Oct 5, 2026

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Palo Alto Networks

Senior ASIC Design Engineer

Office - USA - CA - Headquarters

About the Role Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own …

Added Oct 27, 2026

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Broadcom

ASIC Design - Floorplan Engineer

Fort Collins, Colorado, United States

Full time
Regular

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing …

Added Oct 31, 2026

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Cisco Systems

ASIC Physical Design Engineer

Caesarea, Israel

Cisco Silicon One is seeking a Physical Design Engineer. Meet the Team The Physical Design team within Cisco Silicon One owns backend methodology and flow …

Added Oct 27, 2026

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Marvell Technology

Architecture ASIC Engineer

Córdoba, Cordoba, Argentina

Full time
Regular

Added Nov 3, 2026

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Broadcom

ASIC Verification Engineer

IND-Pune EON Kharadi Infrastructure

Full time
Regular

Added Oct 30, 2026

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Cisco Systems

ASIC DFT Engineer

Austin, Texas, United States +1 location

Pay posted by employer$139,300–$203,600

Added Oct 29, 2026

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Broadcom

ASIC VERIFICATION ENGINEER

Bengaluru, Karnataka, India

Full time
Regular

Added Oct 5, 2026

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Micron Technology

STAFF ASIC Design Engineer

Hsinchu - Chang Yih, Taiwan

… Expertise in RTL and/or testbench development using Verilog/SystemVerilog. Solid understanding of Digital ASIC Design methodology. Experience in large-scale design projects. Familiarity with standard ASIC design flow …

Added Nov 3, 2026

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Nvidia

ASIC Verification Engineer - Clocks

Bengaluru, Karnataka, India

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed …

Added Oct 27, 2026

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Cisco Systems

ASIC Design Verification Engineer

San Jose, California, United States

Pay posted by employer$155,000–$222,600

… experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC Layout Engineer

Armenia

We are hiring an ASIC Engineer to own standard cell layout for our next-generation ASICs on innovative FinFET and GAA nodes. You will …

Added Oct 28, 2026

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Nvidia

Senior ASIC Verification Engineer

Austin, Texas, United States

… human inventiveness and intelligence. The NVIDIA System-On-Chip (SOC) group is looking for an experienced ASIC Verification Engineer! In this position you will have the chance to create a high-level and broad impact at …

Added Oct 27, 2026

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Broadcom

ASIC Implementation Engineer PD

San Jose, California, United States

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

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Preferred qualifications · employer excerpt

Bachelors degree in Electrical Engineering and 8+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
Or Master's degree in Electrical Engineering and 6+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet etc)
Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes
Proven track record with bump planning, RDL implementation, and multi-voltage domain designs

4 more in the full description below.

About this opportunity

Original employer description

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Job Description:

Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Products. More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.

Responsibilities:

Own chip floor planning, partition creation, clock tree and delivery of top level partitions
Resolve physical design issues related to chip integration and assembly
Manage all cross functional interactions related to top level floorplanning, I/O and bump planning with package team
Develop and improve floorplan implementation methodologies using both industry and internal tools
Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specification

Preferred qualifications:

Bachelors degree in Electrical Engineering and 8+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
Or Master's degree in Electrical Engineering and 6+ years of experience in top level floorplannning with a focus on die size estimate, partitioning, clocking and pin planning
Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet etc)
Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes
Proven track record with bump planning, RDL implementation, and multi-voltage domain designs
Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, custom routes and bump planning
Experience in collaborating with design, package and methodology teams during development phase
Experience in scripting languages like Python, Tcl, or Perl and EDA tools
Must work in person at our San Jose site and no remote work option

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Why this result? · Employer labels

All keywords in title

Full time
R&D
Regular

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.