1,000+ matching jobs for “Physical Design Engineer”

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Intel

GPU Design Verification Engineer

Bengaluru, Karnataka, India

Full time
Regular

The Role and Impact: We are looking for a GPU Design Verification Engineer to ensure the functional accuracy of cutting-edge graphics logic components, …

Added Oct 27, 2026

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Analog Devices

Senior Digital Design Engineer

Bengaluru, Karnataka, India +1 location

Own end-to-end physical implementation for major IP blocks and/or full-chip designs, ensuring alignment with ADI’s Career …

Added Nov 3, 2026

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Marvell Technology

Senior Staff Physical Verification CAD Engineer

Singapore

Full time
Regular

… member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to …

Added Nov 3, 2026

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Palo Alto Networks

Senior ASIC Design Engineer

Office - USA - CA - Headquarters

… and help deliver the digital logic that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and physical-design …

Added Oct 27, 2026

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Broadcom

Lead ASIC Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you …

Added Oct 5, 2026

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Intel

Platform Hardware Design Engineer

Malaysia, Penang

Full time
Regular

… from architecture definition through board bring-up, validation, and debug. Responsible for leading the design and development of high-speed printed circuit boards (PCB), subsystems, and platform solutions while …

Added Oct 27, 2026

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Cisco Systems

Senior Circuit Design Engineer

Armenia

Drive the architecture, design, and implementation of high-performance ASIC subsystems and IP from specification through silicon …

Added Oct 31, 2026

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Analog Devices

Associate Analog Design Engineer

Chandler, Arizona, United States +3 locations

Pay posted by employer$68,390–$94,055

As an Associate Analog Design Engineer at Analog Devices, you will contribute to the design and development of analog and mixed-signal …

Added Nov 3, 2026

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Analog Devices

Associate Analog Design Engineer

San Jose, California, United States

Pay posted by employer$82,787–$113,857

As an Associate Analog Design Engineer at Analog Devices, you will contribute to the design and development of analog and mixed-signal …

Added Nov 3, 2026

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Analog Devices

Senior Digital Design Engineer

Munich, Bavaria, Germany

As a Senior Digital Design Engineer, you will drive technical strategy and innovation for complex digital systems, including System on …

Added Nov 3, 2026

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Intel

Platform Hardware design Engineer

Bengaluru, Karnataka, India

Full time
Regular

Position Overview: As a Platform Hardware Design Engineer, you will contribute to the end-to-end development of advanced platform hardware, translating …

Added Oct 27, 2026

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PBF Energy

Engineer, Sr. Process Design

Oregon, Ohio, United States

Full time
Regular

… 1. Project Development: Support the Project Team with project engineering requirements, including process design input, technical reviews, scope definition, and alignment with engineering standards and best practices. …

Added Oct 27, 2026

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Intel

Silicon Packaging Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

Join our team as a Silicon Packaging Design Engineer in the Data Center Group, where you will play a pivotal role in crafting cutting-edge silicon …

Added Oct 27, 2026

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Analog Devices

Staff Design Verification Engineer

United Kingdom, Edinburgh, SC, Freer

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and …

Added Nov 3, 2026

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Nvidia

Mask Design Engineer – Hardware

Santa Clara, California, United States +5 locations

… problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions! This position …

Added Oct 27, 2026

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Nvidia

ASIC Design Engineer - Hardware

Austin, Texas, United States

Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP …

Added Oct 27, 2026

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Marvell Technology

Digital IC Design Engineer

Córdoba, Cordoba, Argentina

Full time
Regular

include: · RTL design/coding. · Testbench simulation and verification. · Debug design issues and ensure functional correctness. · …

Added Nov 3, 2026

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Analog Devices

Analog Design Engineer Intern

Wilmington, Massachusetts, United States +2 locations

Pay posted by employer$22–$41

As an Analog Design Engineer Intern at Analog Devices ( ADI ) , you will have the opportunity to work alongside senior …

Added Nov 3, 2026

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Intel

Analog Circuit Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

Role Overview As an Integrated Voltage Regulator (IVR) Design Engineer, you will be responsible for the architecture, design, and implementation of high-performance …

Added Oct 27, 2026

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Analog Devices

Staff Design Evaluation Engineer

Limerick, Munster, Ireland

Added Nov 3, 2026

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Broadcom

Lead ASIC Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

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Required Qualifications · employer excerpt

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies.

2 more in the full description below.

About this opportunity

Original employer description

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Job Description:

We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you will be the primary technical anchor responsible for the top-level architecture, microarchitecture, and full chip integration. You will guide a cross-disciplinary team spanning analog design, physical design, and verification, owning the design outcome end-to-end from early product definition to a successful foundry tape-out.

Leadership & Strategic Responsibilities

Technical Ownership: Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.
Cross-Discipline Alignment: Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.
Tape-Out Delivery: Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.
Mentorship & Culture: Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team.

Technical Execution Responsibilities

RTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).
Timing & Constraint Ownership: Drive top-level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block-level timing budgets for the PD team.
Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
IP Management: Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP.
Silicon Validation: Collaborate with post-silicon validation and software teams during initial chip bring-up and lab debug phases.

Required Qualifications

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies.
Communication: Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project.
Work Authorization: Must have legal authorization to work in the US.

Preferred & Bonus Skills

Experience with mixed-signal or high-speed PHY-adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects).
Familiarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan.
Proficiency in scripting (Python, Tcl, Perl) to automate and streamline front-end design flows.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $143,800 - $230,000.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Keywords also found in description

Full time
R&D
Regular

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