1,000+ matching jobs for “Design Verification Engineer”

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Broadcom

Foundation IP Design Engineer

Singapore-Yishun

Full time
Regular

We are looking for energetic and passionate memory design engineers to join our Central Engineering Group and be part of an elite memory team responsible for the …

Added Oct 5, 2026

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Broadcom

Lead ASIC Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you …

Added Oct 5, 2026

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Nvidia

ASIC Verification Engineer - New College Grad 2027

Santa Clara, California, United States

… Come join the team and see how we can make a lasting impact on the world. We are seeking to hire a ASIC Verification Engineer - New College Grad 2027 to contribute to the design verification activities that support the …

Added Oct 27, 2026

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Intel

Staff Logic Design Engineer

Malaysia, Penang 2 postings

… engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build …

Added Oct 27, 2026

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Thermo Fisher Scientific

Systems Design Engineer - Bioengineering

Pleasanton, California, United States

Pay posted by employer$107,800–$143,800

… scientists and engineers, this person will contribute to system definition, architecture, integration and verification across instruments, consumables, assays, software and data. Location This is a fully onsite role based at …

Added Oct 31, 2026

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Nvidia

Senior ASIC Design Engineer

Santa Clara, California, United States +1 location

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity …

Added Oct 27, 2026

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Nvidia

CPU Design Methodology Engineer

Hillsboro, Oregon, United States +3 locations

We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now …

Added Oct 27, 2026

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RTX

Senior FPGA Design Engineer

Tucson, Arizona, United States

… a safer, more secure world. Join us and help shape the future of aerospace and defense. As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, …

Added Oct 27, 2026

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RTX

Senior FPGA Design Engineer

Tewksbury, Massachusetts, United States

Added Oct 27, 2026

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Intel

Senior DFT Design Engineer

Folsom, California, United States +3 locations

Pay posted by employer$141,910–$172,860 USD per year

… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …

Added Nov 4, 2026

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RTX

FPGA Design Engineer II

Tucson, Arizona, United States

… threat. Our team solves tough, meaningful problems that create a safer, more secure world. As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device families including: Xilinx, …

Added Oct 27, 2026

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RTX

Senior RF Design Engineer

El Segundo, California, United States

The RF/Microwave Antenna Engineer will contribute to the development of advanced circulators, radiators, filters, and other passive …

Added Oct 27, 2026

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Boeing

Software Test & Verification Engineer (Experienced or Senior)

USA - Albuquerque, NM +1 location

In person
Full time
Regular

Pay posted by employer$104,550–$151,800

… Develops, automates, tests, integrates, and administers emulation strategies and technologies Develops verification plans, test procedures and test environments, executing the test procedures and documenting test results …

Added Oct 12, 2026

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Intel

Analog Circuit Design Engineer

Bengaluru, Karnataka, India

Role Overview As an Integrated Voltage Regulator (IVR) Design Engineer, you will be responsible for the architecture, design, and implementation of high-performance …

Added Oct 27, 2026

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GE Vernova

Engineer 1 - Transformer Design Engineer

Clearwater, Florida, United States

Pay posted by employer$80,000–$120,000

Summary We are seeking an independent Design Engineer to join our team. This role is pivotal in the production design of instrument transformers and …

Added Nov 3, 2026

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Nvidia

Senior Circuit Design Engineer

Santa Clara, California, United States

We are now hiring for a Senior Circuit Design Engineer for Standard Cell and/or ROM. NVIDIA has been transforming computer graphics, PC gaming, and …

Added Oct 31, 2026

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Analog Devices

Senior Digital Design Engineer

Munich, Bavaria, Germany

As a Senior Digital Design Engineer, you will drive technical strategy and innovation for complex digital systems, including System on …

Added Nov 3, 2026

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Micron Technology

Principal Design Engineer, HBM

Richardson, Texas, United States

Design Ownership: Work on HBM product design and own design health through sustaining phase, driving ECO …

Added Nov 3, 2026

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RTX

Senior FPGA Design Engineer

US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A

… missiles/effectors, radars, and electronic warfare systems. The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production …

Added Oct 27, 2026

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Nvidia

Senior Physical Design Engineer

Santa Clara, California, United States +1 location

We are now looking for a Senior Physical Design Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 …

Added Oct 27, 2026

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Broadcom

Lead ASIC Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 per year

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Required Qualifications · employer excerpt

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies.

2 more in the full description below.

About this opportunity

Original employer description

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Job Description:

We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you will be the primary technical anchor responsible for the top-level architecture, microarchitecture, and full chip integration. You will guide a cross-disciplinary team spanning analog design, physical design, and verification, owning the design outcome end-to-end from early product definition to a successful foundry tape-out.

Leadership & Strategic Responsibilities

Technical Ownership: Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.
Cross-Discipline Alignment: Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.
Tape-Out Delivery: Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.
Mentorship & Culture: Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team.

Technical Execution Responsibilities

RTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).
Timing & Constraint Ownership: Drive top-level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block-level timing budgets for the PD team.
Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
IP Management: Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP.
Silicon Validation: Collaborate with post-silicon validation and software teams during initial chip bring-up and lab debug phases.

Required Qualifications

Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies.
Communication: Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project.
Work Authorization: Must have legal authorization to work in the US.

Preferred & Bonus Skills

Experience with mixed-signal or high-speed PHY-adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects).
Familiarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan.
Proficiency in scripting (Python, Tcl, Perl) to automate and streamline front-end design flows.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $143,800 - $230,000.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Keywords also found in description

Full time
R&D
Regular

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