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Fort Collins, Colorado, United States 2 postings
Pay posted by employer$61,900–$99,000 USD per year
Be part of the IC design team within Broadcom ASIC Products Division in beautiful Fort Collins, Colorado, where we create CMOS ASIC's for industry leading AI, …
Singapore-Yishun 6 postings
We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing …
San Jose, California, United States 2 postings
Pay posted by employer$143,800–$230,000 USD per year
Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, …
Fort Collins, Colorado, United States
Pay posted by employer$109,700–$175,500 USD per year
Job Description : Broadcom is a world leader in custom ASIC design including but not limited to cutting edge AI solutions. Broadcom is in search of a Reliability …
McKinney, Texas, United States
… Identify and manage project risks and opportunities. Create complete documentation including requirements, verification plan, and user’s guides Lead medium sized teams to success. Coach, review, and delegate work to junior …
San Jose, California, United States
Pay posted by employer$82,500–$132,000 USD per year
Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We …
San Jose, California, United States
Pay posted by employer$82,500–$132,000 USD per year
Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We …
Bengaluru, Karnataka, India
… fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal Engineer-DFT with Marvell, you’ll be a member of the Connectivity business group. Connectivity solutions from …
Bengaluru, Karnataka, India
… at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We are looking for …
Tel Aviv, Tel Aviv, Israel
… and enterprise networks. Cisco's silicon team provides an outstanding, unique experience for Software and ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large …
McKinney, Texas, United States
… Concept of Operations (CONOPS). Design and code in VHDL for reliability and maintainability. Support design verification utilizing self-checking techniques with directed and constrained random tests, while tracking functional …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 USD per year
This individual will be a key member of the ASIC system-level verification team. Responsibilities include developing complex verification environments, …
Armenia
… groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
… architecture and design through production and sustainment. The MPD department is seeking a Principal FPGA Engineer to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions …
Santa Clara, California, United States
… of innovation that's fueled by phenomenal technology—and outstanding people! We are seeking a world-class engineer to drive applied research at the intersection of AI and ASIC design. Large language models, coding agents, …
Bengaluru, Karnataka, India
… position requires a breadth of disciplines and responsibilities in supporting the Processor based subsystem verification for the ‘ASIC Products Division’ within Broadcom Limited. Responsibilities will include Verification …
San Jose, California, United States +3 locations
Pay posted by employer$121,900–$195,000 USD per year
… partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able drive tools and methodologies to achieve desired PPA metrics. Candidate would …
Singapore-Yishun
Job Description 1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key …
Hillsboro, Oregon, United States +3 locations
We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now packing tens of …
Santa Clara, California, United States
… at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
