704 matching jobs for “IC Design Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Analog Devices

Mixed Signal Design Engineer

Limerick, Munster, Ireland

As a Mixed Signal Design Engineer, you will be responsible for designing and developing mixed-signal integrated circuits, including …

Added Nov 3, 2026

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Capital One Financial

Full-stack Engineer 5 (Senior Manager, IC)

McLean, Virginia, United States +2 locations

… across multiple teams, shaping system architecture and long-term technology direction Drive end-to-end design and implementation of large-scale, distributed, or cloud-native systems with high reliability and …

Added Oct 27, 2026

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Capital One Financial

Full-stack Engineer 5 (Senior Manager, IC)

McLean, Virginia, United States +2 locations

Added Oct 27, 2026

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Capital One Financial

Full-stack Engineer 5 (Senior Manager, IC)

New York City, New York, United States +2 locations

Added Oct 27, 2026

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Nvidia

ASIC Physical Design Engineer

China, Shanghai

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design …

Added Oct 27, 2026

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KLA

Opto-Mechanical Design Engineer (Precision Mechanism Design)

Milpitas, California, United States

Full time
Regular

Pay posted by employer$117,800–$200,300 per year

… devices to volume production quickly and cost-effectively. Enabling the movement towards advanced chip design, KLA's Global Products Group (GPG), which is responsible for creating all of KLA’s metrology and inspection …

Added Oct 15, 2026

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Capital One Financial

Full-stack Engineer 5 (Senior Manager, IC)

McLean, Virginia, United States +1 location

Added Oct 27, 2026

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KLA

Sr. Systems Design Engineer

Milpitas, California, United States 2 postings

Full time
Regular

Pay posted by employer$159,500–$271,200 per year

Added Oct 15, 2026

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Broadcom

I/O Design Engineer

Singapore-Yishun

Full time
Regular

Role Overview Broadcom’s Central Engineering Group is seeking an I/O Design Engineer with experience in analog and mixed-signal IC design. The candidate will contribute to the design …

Added Oct 5, 2026

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Capital One Financial

Full-stack Engineer 4 (Lead/Manager IC)

New York City, New York, United States

… AWS tools and services Provide technical leadership and direction across Agile teams, setting standards for design, development, and operational excellence Partner with architects to define service boundaries, integration …

Added Oct 27, 2026

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Capital One Financial

Full-stack Engineer 4 (Manager, IC)-EDT

McLean, Virginia, United States +2 locations

Added Oct 27, 2026

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Capital One Financial

Full-stack Engineer 4 (Manager, IC)-EDT

Richmond, Virginia, United States +1 location

Full-stack Engineer 4 (Manager, IC)-EDT Do you love building and pioneering in the technology space? Do you enjoy solving …

Added Oct 27, 2026

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KLA

Senior Mechanical Design Engineer

Milpitas, California, United States

Full time
Regular

Pay posted by employer$141,300–$207,233 per year

… business priorities by delivering high-impact work across your area of expertise. The Sr. Mechanical Design Engineer is responsible for developing innovative mechanical design solutions that meet demanding …

Added Oct 15, 2026

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Capital One Financial

Machine Learning Engineer 5 (Senior Manager, IC)

New York City, New York, United States +4 locations

… role, you'll be expected to perform many ML engineering activities, including one or more of the following: Design, build, and/or deliver ML models and components that solve real-world business problems, while working in …

Added Oct 28, 2026

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Capital One Financial

Machine Learning Engineer 5 (Senior Manager, IC)

Chicago, Illinois, United States

Added Oct 27, 2026

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Baker Hughes

Electrical/Electronics Design Engineer

IN-Maharashtra-Pune-7th Floor, Tower 1 & 2, Phoenix Millenium Towers S No. 132, 23. Pune-Bangalore Highway

Full time

in a team of early and mid-career engineers. As an Electrical Engineer, you will be responsible for: • Leading a team of early to mid-career electrical engineers on electrical …

Added Oct 27, 2026

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Capital One Financial

Machine Learning Engineer 5 (Senior Manager, IC)

McLean, Virginia, United States +1 location

Added Oct 27, 2026

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Broadcom

I/O Design Engineer

Chandler, Arizona, United States

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

Role Overview Broadcom’s Central Engineering Group is seeking an I/O Design Engineer with experience in analog and mixed-signal IC design. The candidate will contribute to the design …

Added Oct 5, 2026

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Broadcom

Design Engineer - Timing Methodology

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

… and take ownership in Advanced Timing Sign-off methodology development and modeling for SOC and 3D/2.5D IC design. This includes complex studies and analysis of new concepts leading to design, development and …

Added Oct 5, 2026

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Broadcom

Systems Engineering Analog IC Validation

Colorado Springs, Colorado, United States

Full time
Regular

Pay posted by employer$91,100–$146,000 USD per year

Analog IC Validation Job Description The Analog IC Validation team is responsible for defining, developing, and …

Added Oct 15, 2026

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Broadcom

Design Engineer - Timing Methodology

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

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Qualifications · employer excerpt

The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+ years of industry experience.
Strong hands-on experience in Timing Signoff methodology development and ownership.
Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.
Strong hands-on experience with statistical data analysis and modeling.
Strong hands-on experience in silicon technologies, testability and yield.

11 more in the full description below.

About this opportunity

Original employer description

Please Note:

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Job Description:

Broadcom's Timing Sign-Off group in Central Engineering is looking for an energetic and self-driven professional to join our team. Our group’s mission is to provide advanced timing sign-off methodologies to Broadcom’s chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins. The candidate will participate and take ownership in Advanced Timing Sign-off methodology development and modeling for SOC and 3D/2.5D IC design. This includes complex studies and analysis of new concepts leading to design, development and improvement of existing and new solutions. The candidate should have experience in methodology development with deep knowledge of advanced silicon technologies, production testability and yield. The candidate should have Tapeout experience in high volume / high yield complex SOCs at advanced technology nodes. The candidate will be working closely with other experts across the company in a fast paced project oriented agile environment.

The candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. The candidate will be expected to work across multiple facets of projects and juggle multiple responsibilities at the same time.

Responsibilities:

Develop and deploy timing signoff methodologies for advanced technology nodes.
Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions.
Participate & Lead in EDA flow development for Primetime, Tempus & Innovus.

Qualifications:

The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+ years of industry experience.

Strong hands-on experience in Timing Signoff methodology development and ownership.

Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.

Strong hands-on experience with statistical data analysis and modeling.

Strong hands-on experience in silicon technologies, testability and yield.

Strong hands-on experience with industry standard STA tools such as Primetime and Tempus.

Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation.

Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.

Strong analytical skills and extremely detail oriented, organized and methodical.

Strong communication skills. Clear and concise.

Strong multitasking and context switching skills.

Optimistic yet pragmatic attitude.

Demonstrable skills for quick ramp-up.

Ability to stay calm under extreme pressure.

Team player.

Able to work with minimum supervision, handle ambiguity and drive problem solving to resolution autonomously.

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Why this result? · Employer labels

Keywords also found in description

Full time
R&D
Regular

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