316 matching jobs for “ASIC Verification Engineer”

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Cisco Systems

Layout ASIC Engineer

Bengaluru, India

We are looking for a talented and motivated Layout Engineer to join Cisco’s Client Optics Group (COG) Engineering Team. In this role, you will support the physical …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer

US, CA, Santa Clara +1 location

We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. …

Added Oct 27, 2026

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Broadcom

IC Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Responsibilities: Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these …

Added Oct 5, 2026

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Senior ASIC Design Engineer

Vancouver, Washington, United States

Full time
Reg Employee

Pay posted by employer$116,150–$182,400 USD per year

Lead functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, verification, silicon validation, and qualification. Proactively work with other …

Added Oct 12, 2026

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Nvidia

Senior ASIC Design Engineer

US, CA, Santa Clara

will include architecture and micro-architecture design, RTL design and synthesis, and logic and timing verification using pioneering CAD tools and semiconductor process technologies. In addition to the design role, you will …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineer- CAD

San Jose, California, United States

Pay posted by employer$155,000–$222,600

… users. Support releases, tool qualification, and regression signoff. Collaborate with DFT Design, ATPG, Verification, Physical Design, and CAD teams. Minimum Qualifications: Bachelor’s degree in Electrical or Computer …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer

US, CA, Santa Clara

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. …

Added Oct 27, 2026

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Nvidia

Senior Verification Engineer, SoC

US, CA, Santa Clara +4 locations

NVIDIA is seeking an exceptional Senior SoC ASIC Verification Engineer to confirm the functionality of the world’s most powerful AI-enabled SoCs. These SoCs power self-driving …

Added Oct 27, 2026

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Nvidia

ASIC Physical Design Engineer

China, Shanghai

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer

US, CA, Santa Clara +1 location

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the …

Added Oct 27, 2026

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Palo Alto Networks

Senior ASIC Design Engineer

Office - USA - CA - Headquarters

About the Role Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own …

Added Oct 27, 2026

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Cisco Systems

ASIC Physical Design Engineer

Caesarea, Israel

Cisco Silicon One is seeking a Physical Design Engineer. Meet the Team The Physical Design team within Cisco Silicon One owns backend methodology and flow …

Added Oct 27, 2026

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Broadcom

Principal Physical Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — Physical Design …

Added Oct 25, 2026

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Cisco Systems

Senior ASIC Layout Engineer

Armenia

We are hiring an ASIC Engineer to own standard cell layout for our next-generation ASICs on innovative FinFET and GAA nodes. You …

Added Oct 28, 2026

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Cisco Systems

ASIC Physical Design Engineer

Armenia

… and routing. Optimize power, performance, and area while maintaining design correctness through formal verification. Execute static timing analysis, physical verification, formal checks, and signoff closure to ensure …

Added Oct 27, 2026

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Nvidia

Senior Physical Verification Engineer

Israel, Tel Aviv +1 location

… debug, and the ability to scale best practices across multiple programs. This is a great match for an engineer who wants to combine technical depth with broad project impact. What you’ll be doing: Own physical …

Added Oct 27, 2026

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Cisco Systems

Senior Design Verification Engineer

Belgrade, Serbia

Meet the Team Join our SiliconOne team in Serbia, specializing in ASIC functional verification for Cisco Silicon One chips—high-performance networking chips utilized by major …

Added Oct 27, 2026

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Boeing

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$98,600–$133,400

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead) Company: …

Added Oct 12, 2026

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Nvidia

ASIC Design Engineer - Hardware

US, TX, Austin

Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering …

Added Oct 27, 2026

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Cisco Systems

ASIC DFT Engineer

Austin, Texas, United States +1 location

Pay posted by employer$139,300–$203,600

… Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development - Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post …

Added Oct 29, 2026

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Cisco Systems

Layout ASIC Engineer

Bengaluru, India

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Who You Are · employer excerpt

Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)

About this opportunity

Original employer description

What You'll Do

We are looking for a talented and motivated Layout Engineer to join Cisco’s Client Optics Group (COG) Engineering Team. In this role, you will support the physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions.

You will contribute to all phases of physical design—from concept through tapeout—primarily for block-level layouts while assisting with top-level integration. Working closely with circuit designers, packaging engineers, process teams, and product engineers, you will help develop robust, manufacturable layouts that meet performance, reliability, area, and schedule goals.

Specific responsibilities include:

Support layout development and physical implementation of analog, mixed-signal circuits, high-speed interfaces (including SerDes and PAM4), and supporting digital blocks

Participate in block-level floorplanning, placement, routing, and integration for complex mixed-signal ICs

Collaborate with circuit designers to translate schematics and performance targets into optimized physical layouts

Optimize layouts for electrical performance, matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability

Ensure compliance with all foundry design rules (DRC, LVS, ERC, density, EM/IR, and reliability requirements)

Assist in integration across analog, digital, and high-speed domains, including support for top-level assembly of SerDes, PAM4 paths, clocking, and control logic

Review post-layout extraction results and support simulation closure

Follow best practices for symmetry, shielding, isolation, and signal integrity

Partner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration

Identify and help resolve layout-related issues impacting performance, yield, or production readiness

Participate in layout reviews and provide input on feasibility, tradeoffs, and tapeout risks

Collaborate with CAD teams to improve layout flows, automation, and productivity

Support tapeout readiness, including database checks and signoff

Assist senior engineers with mentoring more junior layout team members and adopt strong layout methodology

Support silicon bring-up, debug, and failure analysis for layout-related issues

Who You’ll Work With

As a Layout Engineer in the Client Optics Group (COG) Engineering Team, you will collaborate with a multidisciplinary team including analog/mixed-signal circuit designers, digital designers, verification engineers, package engineers, process technologists, CAD specialists, reliability experts, and post-silicon validation teams.

You will partner with architects and designers during concept and planning phases, contribute to layout execution during design, work with signoff teams prior to tapeout, and support debug efforts post-silicon when layout-related issues arise. This role is a great opportunity to grow while helping deliver high-speed electrical IPs such as SerDes, PAM4 interfaces, D2D PHY, clocking subsystems, and control logic.

Who You Are

Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)

4-6 years of experience in custom IC layout for analog, mixed-signal, and high-speed designs

Solid technical skills with an interest in growing into layout leadership; strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity

Good knowledge of device-level layout techniques (common-centroid, interdigitation, guard rings, isolation structures)

Proficiency with industry-standard tools such as Cadence Virtuoso and Calibre (or equivalent)

Understanding of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows

Familiarity with ASIC/SoC tapeout processes is preferred

Experience with scripting (Python, Perl, or TCL) for layout automation is a plus

Comfortable working in Linux environments

Excellent analytical, problem-solving, communication, and teamwork skills

Demonstrated ability to contribute effectively and grow as a technical leader in a fast-paced environment

Ability to work as a team player with cross-functional teams spread across geo-locations.

Minimum Qualifications

Bachelor’s or Master’s in Electrical Engineering or equivalent field

3+ years of layout design experience in analog, mixed-signal, or high-speed IC development

Hands-on experience supporting block-level layout efforts through tapeout

Strong skills in custom layout design, physical verification, and parasitic-aware implementation

Experience with Cadence or similar custom layout tools

Why Cisco

WE ARE CISCO

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it.

We embrace digital and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. A blockchain company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box!

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)

Day to day, we focus on the give and take. We give our best, we give our egos a break and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward.

So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Disclaimer

To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:

be in direct response to an application you have submitted through the company career site
begin with screening or an interview
originate from a Cisco email address, and
be conducted across email, phone, or WebEx

Cisco will never make a job offer without conducting an interview process or ask you for money in any way. If you have been requested to apply for a role or have received an offer from a site other than https://careers.cisco.com or cisco.wd5.myworkday.com, do not provide any personal identifying information, including your Aadhaar or other personal identifying number, birth certificate, banking information, driver's license, or passport.

If you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.

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