668 matching jobs for “ASIC Engineer”

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Nvidia

Verification Engineer, PCIE

Bengaluru, Karnataka, India

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s …

Added Oct 27, 2026

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Broadcom

IC Verification Engineer

San Jose, California, United States 2 postings

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

… developing Test plans, Functional coverage and pseudo-random testing Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification Very proficient in …

Added Oct 14, 2026

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Broadcom

Design Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

The ASIC Product Division at Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for …

Added Oct 23, 2026

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Broadcom

Design Implementation Engineer

San Jose, California, United States +3 locations

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

… fly. Excellent communication skills. Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must. Should have worked on tape out of at least 1-2 ASIC's in 7nm or lower technologies …

Added Oct 20, 2026

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Nvidia

Senior DFT Engineer

Santa Clara, California, United States

… safety platforms etc. Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI, SW development, and Operations teams to productize new methodologies Help …

Added Oct 27, 2026

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GE Aerospace

Staff Engineer - FPGA Design/Verification

Grand Rapids, Michigan, United States +2 locations

Full time
Regular

Summary GE Aerospace is seeking an experienced Staff Engineer – FPGA Design/Verification to lead the development of custom logic for advanced avionics hardware. This …

Added Oct 27, 2026

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Intel

Logic Design Engineer

Malaysia, Penang

Full time
Regular

… talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build world-changing …

Added Oct 27, 2026

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Broadcom

Package Design Engineer

San Jose, California, United States +2 locations

Full time
Regular

Pay posted by employer$82,500–$132,000 USD per year

Broadcom is seeking an IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power …

Added Oct 5, 2026

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Broadcom

Package Design Engineer

San Jose, California, United States +2 locations

Full time
Regular

Pay posted by employer$101,000–$162,000 USD per year

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power …

Added Oct 5, 2026

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Analog Devices

Staff DFT Engineer

Bengaluru, Karnataka, India

… of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow. Excellent problem-solving skills, with the ability to troubleshoot and resolve complex DFT …

Added Nov 3, 2026

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Nvidia

Senior Formal Verification Engineer - LPU

US, CA, Remote +4 locations

… work. Join us and discover how you can build a lasting impact on the world! As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the forefront using formal verification tools. You will …

Added Oct 31, 2026

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Marvell Technology

Senior Staff Hardware Engineer

Taipei

Full time
Regular

… Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Hardware Design Senior Staff Engineer will serve as a key member of the Hardware Design team within the Operations PE/TE organization. This role …

Added Nov 3, 2026

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Nvidia

Senior Digital Design Engineer

Santa Clara, California, United States +2 locations

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard working …

Added Oct 31, 2026

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Marvell Technology

Principal Engineer, ATE Test Development Engineer

Santa Clara, California, United States

Full time
Regular

… of experience in Semiconductor Test Engineering, with Demonstrated Technical Leadership on Complex SoC/ASIC/analog Test Programs Strong Hands-on Experience with Advantest 93000 ATE Platforms and SmarTest-8 Test …

Added Nov 3, 2026

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RTX

FPGA Engineer II (ONSITE)

Melbourne, Florida, United States

… market. Join us and help shape the future of aerospace and defense. Collins Aerospace is seeking a FPGA Engineer II for the CNS (Communication, Navigation, Surveillance) Hardware Engineering Group in Melbourne, Florida. …

Added Oct 27, 2026

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Nvidia

Senior STA Signoff Methodology Engineer

Santa Clara, California, United States +1 location

… how you can make a lasting impact on the world. We are seeking an innovative Senior STA Signoff Methodology Engineer to help drive sign-off strategies for the world's leading GPUs, CPUs, LPUs and SoCs. This position is a …

Added Oct 27, 2026

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Nvidia

Senior Physical Verification Engineer

Israel, Tel Aviv +1 location

… debug, and the ability to scale best practices across multiple programs. This is a great match for an engineer who wants to combine technical depth with broad project impact. What you’ll be doing: Own physical …

Added Oct 27, 2026

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Broadcom

Design Engineer - STA

Fort Collins, Colorado, United States

Full time
Regular

Pay posted by employer$129,400–$207,000 USD per year

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing …

Added Oct 5, 2026

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Marvell Technology

Principal Hardware Engineer - 3rd Party IP Engineer

Morrisville, North Carolina, United States +5 locations

Full time
Regular

… in this position, you will engage all parts of Marvell. Looking for a talented 3rd party IP integration engineer to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients. Become part of …

Added Nov 3, 2026

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Broadcom

Design Engineer - STA

Fort Collins, Colorado, United States

Full time
Regular

Pay posted by employer$129,400–$207,000 USD per year

… teams spread across geographical time-zones. Technical Skills/ background Strong understanding of VLSI and ASIC physical design Should have basic understanding of PLLs and clock networks Should be familiar with design …

Added Oct 5, 2026

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Broadcom

Design Implementation Engineer

San Jose, California, United States +3 more

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

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Requirements · employer excerpt

Extremely proficient in design implementation activities both at block and SoC level.
Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification and/ or constraints development, constraints validation, timing analysis and closure.
Experience with formal verification, timing analysis and Eco implementation.
Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime etc is highly desirable.
Full chip tapeout experience based on 7nm and lower technologies is highly preferred.

7 more in the full description below.

About this opportunity

Original employer description

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Job Description:

The candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able drive tools and methodologies to achieve desired PPA metrics. Candidate would also be required to do equivalence checks, STA, Timing closure and power optimization. Should be able to implement timing and functional ECOs.

In this role, the candidate will apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Primary expertise in place and route and/ or timing (constraints, STA) can be considered for this position.

Requirements:

Extremely proficient in design implementation activities both at block and SoC level.
Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification and/ or constraints development, constraints validation, timing analysis and closure.
Experience with formal verification, timing analysis and Eco implementation.
Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime etc is highly desirable.
Full chip tapeout experience based on 7nm and lower technologies is highly preferred.
Good problem solver.
Self starter who can work independently.
Experienced in working in a global team and dynamic environment.
Ability to learn and adapt to new tools and methodologies on the fly.
Excellent communication skills.
Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must.
Should have worked on tape out of at least 1-2 ASIC's in 7nm or lower technologies

Education and Experience required:

BS in Electrical Engineering/ Computer Engineering or related field and 8+ years of related experience or an MS in Electrical Engineering/ Computer Engineering or related field and 6+ years of related experience.

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Keywords also found in description

Full time
R&D
Regular

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