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Pay posted by employer$121,900–$195,000 USD per year
… design partitioning, and block pin assignment. Perform block PnR, timing closure, and physical verification. Perform block IR/EM analysis. Experience with chip level IR/EM analysis is a big plus. Familiar with …
Pay posted by employer$122,440–$172,860 USD per year
… and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this …
Designs and develops integrated circuits. Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system …
Pay posted by employer$143,800–$230,000 USD per year
This individual will be a key member of the ASIC system-level verification team. Responsibilities include developing complex verification environments, creating comprehensive test …
San Jose, California, United States +1 location2 postings
Full time
Regular
Pay posted by employer$121,900–$195,000 USD per year
You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture …
Pay posted by employer$109,700–$175,500 USD per year
… team of innovators to build the next generation of high-tech hardware. As an Analog/RF Layout Engineer, you won’t just watch from the sidelines—you'll be in the trenches of custom IP block design, translating …
The candidate will work on the System Level Simulation and Tx Full Chain Verification for RF Front-End Modules (FEM). This role focuses on the holistic performance of the entire Tx lineup, …
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog. Develop self-checking and reusable test benches from the ground …
NVIDIA is seeking a highly motivated DFT Engineer to join our silicon engineering team. In this role, you will work closely with Design, Test, CAD, and …
Pay posted by employer$109,700–$175,500 USD per year
… ASIC design including but not limited to cutting edge AI solutions. Broadcom is in search of a Reliability Engineer to join Broadcom's Global Operations Quality Assurance Team in Fort Collins, CO. The Reliability team …
NVIDIA is searching for a motivated CAD Engineer to join the Advanced Technology Group. You will support installation of foundry techfiles. You will provide …
We are looking for a skilled DRC Runset Engineer to develop, validate, support, and optimize Design Rule Checking runsets for advanced semiconductor process …
We are looking for a skilled DRC Runset Engineer to develop, validate, support, and optimize Design Rule Checking runsets for advanced semiconductor process …