1,000+ matching jobs for “Design Verification Engineer”

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Nvidia

GPU Core Pipeline IP Verification Engineer

Bengaluru, Karnataka, India

NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the …

Added Oct 27, 2026

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Broadcom

Physical Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$82,500–$132,000 USD per year

Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time …

Added Oct 31, 2026

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Broadcom

Physical Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$82,500–$132,000 USD per year

Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time …

Added Oct 31, 2026

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Micron Technology

Staff Design Engineer

San Jose, California, United States

Pay posted by employer$145,000–$246,000 per year

… deliver required functionalities Participate in the conception and development of new circuits Define and design composition architecture specifications for new features. Support the creation of schematics and/or RTL …

Added Nov 3, 2026

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Nvidia

Formal Verification Engineer - New College Graduate

Hungary, Budapest

We are looking for a Formal Verification Engineer within our Hardware team! As a Formal Verification Engineer at NVIDIA, you will verify the design …

Added Oct 27, 2026

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Broadcom

IC Design Engineer

Bengaluru, Karnataka, India 3 postings

Full time
Regular

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous …

Added Oct 5, 2026

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Broadcom

IC Design Engineer

Bengaluru, Karnataka, India 2 postings

Full time
Regular

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous …

Added Oct 5, 2026

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Broadcom

IC Design Engineer

Colorado Springs, Colorado, United States +1 location

Full time
Regular

IC Design Engineer (ICB4) Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions …

Added Oct 21, 2026

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Intel

Circuit Design Engineer

Folsom, California, United States

Pay posted by employer$105,650–$149,150 USD per year

The Role and Impact As a Circuit Design Engineer, you will play a pivotal role in designing and optimizing cutting-edge digital circuits for custom …

Added Oct 27, 2026

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Intel

Logic Design Engineer

Malaysia, Penang

… engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build …

Added Oct 27, 2026

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Baker Hughes

Senior Design Engineer

Houston, Texas, United States

Full time

Senior Design Engineer Do you enjoy working with complex electro-mechanical systems? Do you have experience defining …

Added Oct 28, 2026

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Broadcom

IC Design Engineer

Singapore-Yishun

Full time
Regular

Job Description 1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key …

Added Nov 3, 2026

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Broadcom

ASIC Design Engineer

Fort Collins, Colorado, United States

Full time
Regular

Pay posted by employer$61,900–$99,000 USD per year

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class …

Added Oct 31, 2026

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Boeing

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$98,600–$133,400

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead) Company: The Boeing …

Added Oct 12, 2026

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Broadcom

Physical Design Engineer

Colorado Springs, Colorado, United States +1 location 2 postings

Full time
Regular

Pay posted by employer$129,400–$207,000 USD per year

Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves working with the latest technology …

Added Oct 5, 2026

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Broadcom

Physical Design Engineer

San Jose, California, United States +1 location

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves working with the latest technology …

Added Oct 5, 2026

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Broadcom

Physical Design Engineer

Colorado Springs, Colorado, United States +1 location

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group at our main campus in Colorado Springs, Colorado. This …

Added Oct 5, 2026

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Nvidia

Manager, Software Verification

Israel, Yokneam

NVIDIA is seeking an experienced and technically strong Engineering Manager to lead the DOCA SDK Verification team. The team is responsible for validating the NVIDIA DOCA SDK, ensuring the quality, reliability, and …

Added Nov 3, 2026

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Nvidia

GPU Core Pipeline IP Verification Engineer

Bengaluru, Karnataka, India

NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the …

Added Oct 27, 2026

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Nvidia

IP Verification Engineer - GPU Core Pipeline

Bengaluru, Karnataka, India

NVIDIA is seeking a highly enthusiastic and motivated Verification Engineer to verify the design and implementation of the next generation of control subsystems for the …

Added Oct 27, 2026

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Broadcom

Physical Design Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$82,500–$132,000 USD per year

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Basic Qualifications · employer excerpt

Education: Bachelor's Degree in Electrical Engineering, Computer Engineering + 2yrs of experience or Master’s degree in Electrical Engineering, Computer Engineering (Graduation date within the past 12 months).
Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
Familiarity with static timing analysis (STA) concepts, clocking, and setup/hold timing.
Hands-on coursework, lab experience, or academic projects using EDA design tools (Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools).
Proficient in scripting languages such as TCL, Python, Ruby, or Bash.

About this opportunity

Original employer description

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Job Description:

Physical Design Engineer (New College Grad) — ASIC Products Division (APD)

Location: San Jose, CA

Position Type: Full-Time

Who We Are — Physical Design Team in APD

Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders—to co-design and manufacture complex, custom ASICs that power the modern digital backbone.

The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm/A14 nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success.

What Defines Our Physical Design Team

Pioneering First-Pass Silicon in 3nm/2nm: Our team consistently pushes the boundary of physics, taking the largest and most complex die sizes from floorplan to tapeout on leading-edge foundry nodes (N7, N5, N3, and N2).
Record-Breaking Scale & Complexity: We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors, multi-gigahertz clock frequencies, and dense multi-die 2.5D/3D integration (CoWoS, HBM3/4, chiplet architectures).
Methodology & Flow Leadership: We develop and maintain cutting-edge in-house (AI Driven) automation and methodology across different EDA tools, setting the benchmark for signoff quality and turn-around-time (TAT).

About the Role

Broadcom’s ASIC Products Division (APD) is looking for a motivated Physical Design Engineer (NCG) to join our Physical Design team. In this role, you will work alongside experienced engineers in executing the implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will gain hands-on experience in complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14).

Key Responsibilities

Participate in block-level floorplanning, and run placement and route (P&R) flows using industry-standard EDA tools.
Perform Static Timing Analysis (STA), debug timing paths, and execute ECOs for timing closure.
Run Physical Verification checks (DRC, LVS, ERC, Antenna) and resolve signoff violations.
Analyze IR drop and electromigration (EM) to ensure power grid integrity.
Develop and maintain automated scripts (TCL, Python, Ruby) to enhance flow efficiency and productivity

Basic Qualifications

Education: Bachelor's Degree in Electrical Engineering, Computer Engineering + 2yrs of experience or Master’s degree in Electrical Engineering, Computer Engineering (Graduation date within the past 12 months).
Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
Familiarity with static timing analysis (STA) concepts, clocking, and setup/hold timing.
Hands-on coursework, lab experience, or academic projects using EDA design tools (Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools).
Proficient in scripting languages such as TCL, Python, Ruby, or Bash.

Preferred Qualifications

Prior internship or research experience in ASIC physical design, synthesis, or physical verification.
Basic understanding of Design for Testability (DFT), low-power intent (UPF/CPF), and FinFET technologies.
Excellent problem-solving, debugging, and analytical skills.

Work Authorization / Eligibility Requirements

Legal authorization to work in the U.S. is required

Compensation and Benefits

The annual base salary range for this position is USD 82,500.00 To USD 132,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Keywords also found in description

Full time
R&D
Regular

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