383 matching jobs for “ASIC Verification Engineer”
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Santa Clara, California, United States +1 location
… world. This is our life’s work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone …
… more secure world. Join us and help shape the future of aerospace and defense. As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and …
… more secure world. Join us and help shape the future of aerospace and defense. As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and …
… GPUs and SOCs on standard FPGA prototyping platforms. We are now looking for a Senior FPGA Prototyping Engineer to join our Emulation team onsite in Santa Clara, CA. What you'll be doing: Build FPGA prototypes by making …
… Our team solves tough, meaningful problems that create a safer, more secure world. As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and …
… defense. Join our Advanced Processing Architectures organization as a Principal Embedded Platform Software Engineer, where you will influence the design, development, and integration of the foundational software that …
… Your Impact You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts. You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place …
… creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling …
… closure, synthesis, and lab bring-up, collaborating closely with cross-functional software, hardware, and verification teams. What You’ll Do Write comprehensive micro-architecture and functional specifications for FPGA, CFPGA, …
Pay posted by employer$121,900–$195,000 USD per year
You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture …
… human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a growing and …
Santa Clara, California, United States +1 location
… delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include …
… human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a growing and …
… Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal, Digital IC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the high performance …
Santa Clara, California, United States +1 location
Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed …
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …