397 matching jobs for “ASIC Verification Engineer”
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… creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling …
… closure, synthesis, and lab bring-up, collaborating closely with cross-functional software, hardware, and verification teams. What You’ll Do Write comprehensive micro-architecture and functional specifications for FPGA, CFPGA, …
Pay posted by employer$121,900–$195,000 USD per year
You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture …
… human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a growing and …
Santa Clara, California, United States +1 location
… delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include …
… human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a growing and …
… Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal, Digital IC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the high performance …
Santa Clara, California, United States +1 location
Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed …
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
We are now looking for a Senior Post-Silicon Validation Engineer to join our team! NVIDIA has continuously reinvented itself over the past two decades. Our invention of the …
Pay posted by employer$122,440–$232,190 USD per year
… demanded by modern AI workloads. Position Overview We are seeking an experienced design automation engineer passionate about driving innovation at the intersection between emerging semiconductor technology, physical …
We are looking for a talented Senior System Software Engineer to help build NVIDIA Halos, our full-stack safety platform for physical AI: autonomous vehicles, humanoids, …
Pay posted by employer$164,470–$232,190 USD per year
… digital lives. Come join us and do something wonderful. The Role and Impact: As a GPU Physical Design Engineer, you will play a critical role in the physical implementation of cutting-edge GPU designs from RTL to GDS, …
… and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, IO planning and …
… Design, implement, and maintain high-reliability embedded firmware in C (and C++) for microcontroller- and ASIC-based controllers operating in optical modules at 100G/s and above. Implement Device Diagnostics & Control: …
Santa Clara, California, United States +1 location
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and …