IC Design Engineer
Singapore-Yishun
- Full time
- Regular
Job Description 1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key …
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Singapore-Yishun
Job Description 1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key …
Hillsboro, Oregon, United States +3 locations
We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now packing tens of …
Santa Clara, California, United States
… at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
… and design through production and sustainment. The MPD department is seeking a Senior FPGA Design Engineer to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions …
US-CA-San Jose, California +1 location
Job Description What candidate will Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT …
Malaysia, Penang
… talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build world-changing …
Santa Clara, California, United States +2 locations
We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard working …
Israel, Yokneam +1 location
… at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are …
Bengaluru, Karnataka, India +1 location 3 postings
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, …
IND-Pune EON Kharadi Infrastructure
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India 2 postings
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India
GPU Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation for Media …
Tucson, Arizona, United States
… over the world, from the ground to exoatmospheric environments and into space. As a Principal FPGA Design Engineer you will develop FPGA designs for all major vendors and device families including: Xilinx, Altera, and …
Phoenix, Arizona, United States +2 locations
Pay posted by employer$128,880–$245,160 USD per year
… of life. Join us and help make the future more wonderful for everyone. We are looking for an experienced engineer to join the PDK Reliability Verification / EMIR team. This role will contribute to the development, …
Santa Clara, California, United States +1 location
… adoption by joining NVIDIA's Advanced Technology Group! We are looking for a Full-Chip RTL Integration Engineer to join our dynamic and growing FE-ASIC development team. In this role, you will be responsible for …
Bengaluru, Karnataka, India
… fault (TDF) models using on-chip test compression techniques. MBIST Design (including repair) and Verification using Siemen’s EDA tool. Validation of DFT structures/patterns in RTL, Netlist with and without SDF. Work …
Marlborough, Massachusetts, United States
Requirements capture, FPGA digital architecture and design using RTL, timing closure, verification, and system integration Optimize FPGA implementations to meet performance, power, and size constraints. …
San Jose, California, United States +3 locations
Pay posted by employer$143,800–$230,000 USD per year
… partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Drive tools and methodologies to achieve desired PPA metrics. Complete equivalence checks, STA, …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
… from architecture and design through production and sustainment. The MPD department is seeking an FPGA Engineer II to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.