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Fort Collins, Colorado, United States +1 location
Pay posted by employer$121,900–$195,000 USD per year
… for developing thermal management and robust socketing solutions for test and validation PCBs for Broadcom ASIC products targeted at hyperscale data center applications. Broadcom’s market leading products are enabling …
US, CA, Remote +5 locations
… At NVIDIA, we value innovation, collaboration, and excellence. Join our outstanding team as a Senior Formal Verification Engineer and be at the forefront of developing modern technology that builds the future. This role offers …
Grand Rapids, Michigan, United States +2 locations
Summary GE Aerospace is seeking an experienced Staff Engineer – FPGA Design/Verification to lead the development of custom logic for advanced avionics hardware. This …
Santa Clara, California, United States
We are now looking for a Senior ASIC Design Engineer to join our DFT team! NVIDIA has continuously reinvented itself over two decades. Our …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
You will support requirements capture and ASIC / FPGA digital architecture. You will implement ASIC / FPGA digital design using RTL. You will support …
US-CA-San Jose, California
… with C knowledge Regression & Coverage Closure What We Are Looking For: Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to …
Caesarea, Israel +1 location
Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One …
San Jose, California, United States
Pay posted by employer$155,000–$222,600
include: Support DFT implementation for ASIC / SoC blocks and subsystems Implement and validate scan insertion, scan compression, OCC, MBIST, boundary …
El Segundo, California, United States +1 location
Verification environment architecture and design using SystemVerilog with UVM/UVM-F Creation of written test plan, …
Santa Clara, California, United States +1 location
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The …
Israel, Yokneam +1 location
NVIDIA's Chip Design group is looking for best-in-class Verification Engineers to join our outstanding Silicon Engineering team, developing the industry's best high-speed …
Singapore-Yishun
… of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis). In-depth knowledge of GPU/CPU/DSP architecture/algorithm and …
Singapore-Yishun
… of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis). In-depth knowledge of GPU/CPU/DSP architecture/algorithm and …
Santa Clara, California, United States +4 locations
NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our GPU Memory Subsystem IP verification Team! At NVIDIA, we have crafted a team of …
Bengaluru, Karnataka, India
… cluster and higher-level environments with mix of constraint random and advised stimulus. • Ensure complete verification coverage through implementation and review of code and functional coverage. • Ensure RTL quality with …
Israel, Tel Aviv
NVIDIA is looking for a best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best …
San Jose, California, United States
Pay posted by employer$186,900–$267,700
… methodology. Mentor junior engineers on performing project tasks and problem solving. Collaborate with the verification team to address design bugs and close code coverage. Work closely with physical design team to close design …
Malaysia, Penang
The Role and Impact As a CPU Design Verification Engineer, you will play a pivotal role in ensuring the functionality and reliability of cutting-edge CPU …
Leixlip, Leinster, Ireland
The Role and Impact As a Sr Deep Learning Hardware Verification Engineer, you will play a pivotal role in shaping the future of AI hardware by validating and optimizing …
San Jose, California, United States +1 location
Pay posted by employer$167,700–$245,200
… coding. Prior experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification). Prior experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
