668 matching jobs for “ASIC Engineer”How results work Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
+1 location
… more, and work quickly. Join us to power the future of the digital world. Your Impact Hardware design engineer is a key member of the Cisco Purpose Built Switch hardware team. Define and design the next generation …
Added Oct 27, 2026
DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development …
Added Nov 7, 2026
DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development …
Added Nov 7, 2026
DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California …
Added Nov 7, 2026
DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose. California …
Added Nov 7, 2026
… looking for an experienced, energetic and self-driven professional to join our team as a senior modeling engineer for the development and improvement of functional, timing, power, and DFT simulation models. This role …
Added Nov 11, 2026
… or Masters in CS/ECE with 3+ years of experience. Experience in SDK development in Switching/Routing ASIC is a big plus Hands on experience on switch/router embedded system software development Extensive …
Added Nov 3, 2026
Pay posted by employer $152,500–$219,200
Own and manage day-to-day operation of the hardware lab supporting ASIC bring-up, EVB development, validation, and system debug. Ensure lab readiness for critical milestones such …
Added Oct 27, 2026
Pay posted by employer $91,100–$146,000 USD per year
ASIC Design Engineer Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in …
Added Nov 12, 2026
+4 locations
Pay posted by employer $143,800–$230,000 USD per year
Design Verification Engineer Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and …
Added Oct 5, 2026
Pay posted by employer $129,400–$207,000 USD per year
You will be joining Broadcom's custom silicon division, working on IPs for ASIC products such as custom AI chips. This position is responsible for IP and subsystem verification, including …
Added Nov 12, 2026
Pay posted by employer $109,700–$175,500 USD per year
Job Description : Broadcom is a world leader in custom ASIC design including but not limited to cutting edge AI solutions. Broadcom is in search of a Reliability …
Added Oct 13, 2026
Seeking an experienced PCIe Design Engineer to join Broadcom ASIC Product Division to be part of PCIe subsystems and SoC development. Candidate should …
Added Nov 3, 2026
… and switching platforms. Work also with architecture and design teams to define the next generation of ASIC products being developed. Your Impact As part of Silicon One Software team, you will closely interact with …
Added Oct 30, 2026
Pay posted by employer $82,500–$132,000 USD per year
Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We …
Added Oct 31, 2026
Pay posted by employer $82,500–$132,000 USD per year
Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We …
Added Oct 31, 2026
+1 location
… Define and design the next generation Hyperscaler Switch hardware based on Silicon One and/or merchant ASIC , as well as CPU subsystem. Responsible for system and board level specification, schematic capture, FPGA …
Added Oct 27, 2026
Pay posted by employer $143,800–$230,000 USD per year
Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Austin, Texas Development …
Added Nov 7, 2026
2 postings
Pay posted by employer $143,800–$230,000 USD per year
Principal DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, …
Added Nov 4, 2026
… fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal Engineer -DFT with Marvell, you’ll be a member of the Connectivity business group. Connectivity solutions from …
Added Nov 3, 2026
Qualifications · employer excerpt The minimum engineering experience required is typically a BS degree in EE/CS/CE with programming/coding experience with 8+ years of industry experience, or an MS degree with 6+ or Ph.D. degree in EE/CS with 3+ years of industry experience. Have at least 3 years experience using Linux systems; possess excellent knowledge of Linux commands, file systems, and job execution. Strong preference for 5+ years of experience in Verilog modeling skills Static & Dynamic timing analysis knowledge. Experience with chip design tools and design flows, such as:DFT: Tessent, LogicVision, Modus, manufacturing test flows: at-speed scan test, Logic BIST, Memory BISTSynthesis: Design Compiler, Genus.Simulation: VCS, Questa, Verilog,… 10 more in the full description below.
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Job Description:
Job Description:
Broadcom's Central Engineering Group (CEG) is looking for an experienced, energetic and self-driven professional to join our team as a senior modeling engineer for the development and improvement of functional, timing, power, and DFT simulation models. This role will focus on authoring, debugging, and optimizing memory IP (SRAM, RF, CAM, ROM, etc.) EDA models used in ASIC-like design flows by chip teams throughout the company. This is a senior position with the expectation that the candidate can lead projects, proactively navigate complex technical issues, be able to work autonomously, and collaboratively participate in the establishment of strategic objectives.
The candidate must have abilities to prioritize well, communicate clearly and concisely, deliver high quality solutions on-time, and possess excellent problem solving skills. This person will be expected to work across multiple facets of projects, have experience with ASIC development, and juggle multiple responsibilities at the same time exhibit excellent multitasking, context switching, and time management skills.
Responsibilities:
Candidate will
Lead memory modeling and compiler development projects working closely with design teams in an environment highly charged with technical complexities and dynamic schedule challenges. Be expected to demonstrate skills and abilities to lead and drive results & improvements, multitask and deliver high quality solutions in a timely fashion. Write model templates for integration into memory compilers to generate models used in DFT/CAD tools used in ASIC development flows. Participate in forums for model development, improvement and reviews, and will serve as a knowledge resource for peers, colleagues, and subordinates in the organization. Be expected to communicate well, document well, prioritize tasks and handle the multiple facets of model development projects independently to meet the business goals and commitments. Work to improve memory models and model generation flows for better performance, user experience and quality. Work directly with IP design teams, compiler teams and tool vendors globally to help resolve model related issues, and find timely solutions. Respond to library support requests and address tickets on model issues from product teams across Broadcom.
Qualifications :
The minimum engineering experience required is typically a BS degree in EE/CS/CE with programming/coding experience with 8+ years of industry experience, or an MS degree with 6+ or Ph.D. degree in EE/CS with 3+ years of industry experience. Have at least 3 years experience using Linux systems; possess excellent knowledge of Linux commands, file systems, and job execution. Strong preference for 5+ years of experience in Verilog modeling skills Static & Dynamic timing analysis knowledge. Experience with chip design tools and design flows, such as: DFT: Tessent, LogicVision, Modus, manufacturing test flows: at-speed scan test, Logic BIST, Memory BIST Synthesis: Design Compiler, Genus. Simulation: VCS, Questa, Verilog, waveform viewers, and simulation debug. UVM verification tetsbench and methodology development Conversant with Verilog/RTL/Behavioral/Timing/Power/DFT/ATPG/Synthesizable model development for SRAMs/RF/CAM/ROM, etc. memories. Experience in writing directed test bench in verilog for model verification. Knowledge and experience using simulators - NC, VCS, ModelSim, ESPCV is a must. Familiarity with memory model verification/QC flow is required. Scripting & flow automation, Perl, Python, Tcl, Shell programming skills are required. Able to work in agile and dynamic development environments. Excellent written and verbal communication skills. Skilled multi-tasking abilities and context switching skills are a must. Strong analytical, problem solving and quick learning skills are required. Good team player, methodical, eye for detail, independent, well organized, and have the ability to remain calm and composed in high pressure situations.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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