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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
Bengaluru, Karnataka, India +1 location
… analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust …
Melbourne, Florida, United States
… market. Join us and help shape the future of aerospace and defense. Collins Aerospace is seeking a FPGA Engineer II for the CNS (Communication, Navigation, Surveillance) Hardware Engineering Group in Melbourne, Florida. …
Irvine, California, United States
… trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Digital ASIC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the …
Bengaluru, Karnataka, India
… all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels. What we need to see: BS (or equivalent experience) / MS with 3+ …
Fort Collins, Colorado, United States
Pay posted by employer$129,400–$207,000 USD per year
Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing …
Bengaluru, Karnataka, India
… reviews Cross-Functional Collaboration Work closely with: RTL designers Physical design (PD) Functional verification Product engineering and manufacturing Communicate DFT requirements and risks clearly to stakeholders …
Malaysia, Penang
… talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build world-changing …
Hsinchu, Taiwan, Taiwan +1 location
… life’s work, to amplify human creativity and intelligence. We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling …
Bengaluru, Karnataka, India
GPU Senior Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation for Media …
Fort Collins, Colorado, United States
Pay posted by employer$61,900–$99,000 USD per year
… methodology development to address challenges of designing in deep submicron processes and state-of-the-art ASIC design for AI, computing and networking products Qualifications: Requirements Bachelors in …
Morrisville, North Carolina, United States +5 locations
… in this position, you will engage all parts of Marvell. Looking for a talented 3rd party IP integration engineer to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients. Become part of …
Córdoba, Cordoba, Argentina
… and communication blocks. Create block‑level specifications and documentation. Collaborate with verification teams to define test plans, debug design issues, and ensure functional correctness. Support synthesis, …
Hsinchu City
… and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure …
Santa Clara, California, United States +3 locations
… itself over two decades, inventing the GPU in 1999 to reshape PC gaming and modern computer graphics. As an engineer in our EDA Workflow Optimization team, you will partner closely with our engineering teams worldwide. You …
Santa Clara, California, United States
Are you passionate about DGX systems connecting multiple ASIC chips together, FPGA prototyping, and hardware emulation? Are you interested in pushing the boundaries of …
Santa Clara, California, United States +2 locations
… future of computing. Join our team of hardworking engineers who work across the micro-architecture, design, verification, implementation and post silicon validation of state of the art NVIDIA chips. What you'll be doing: …
McKinney, Texas, United States
will be split between supporting program(s) as a contributing engineer (~75%) and providing functional leadership to the section (~25%). What To Expect As a functional leader, …
Armenia
… understanding of chip architecture. Your primary focus will be to drive high-quality Design for Test (DFT) verification, ensuring robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation. …
Melbourne, Florida, United States
… market. Join us and help shape the future of aerospace and defense. We are looking for a Senior Electrical Engineer - FPGA to join our team in Melbourne, FL. This position will work closely with our Avionics teams to meet …
Santa Clara, California, United States
Are you a Mask Layout Design Engineer? We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
