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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
China, Shanghai
… of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, …
Carlsbad, California, United States +1 location
Pay posted by employer$192,400–$275,800
… Cisco’s industry-defining Silicon One Optics group, you won’t just follow the future of networking—you’ll engineer it. We are actively building the hyper-scalable optical transceivers and modules (800G, 1.6T, and beyond) …
Folsom, California, United States +3 locations
Pay posted by employer$220,920–$311,890 USD per year
… driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs …
US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A
Verification environment architecture and design using SystemVerilog with OVM/UVM Creation of written test plan, …
Bengaluru, Karnataka, India
… networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design verification background with hands-on experience in System …
San Jose, California, United States
Pay posted by employer$186,900–$267,700
… the future of the digital world. Your Impact You will be in the Silicon One development organization as an ASIC DFT STA Technical Lead. You are a detail-oriented STA engineer with strong analytical skills and a deep …
San Jose, California, United States
Pay posted by employer$167,700–$245,200
… RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification. Minimum Qualifications Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or …
San Jose, California, United States +1 location
Pay posted by employer$167,700–$245,200
… ATE screening, in-system test, debug and diagnostics needs of the design Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation …
Armenia
… ATE screening, in-system testing, debugging, and diagnostics. We collaborate closely with design, design-verification, and product development teams to integrate and validate test logic throughout implementation and …
Bengaluru, Karnataka, India +1 location
… power management architecture of next generation chips. One should possess strong digital design and verification fundamentals. What you'll be doing: As a designer, be responsible for making architectural trade-offs based …
Toronto, Ontario, Canada
NVIDIA is seeking a motivated and creative Senior Verification Engineer to join our Tegra SoC IP Verification team. Our mission is to build the IP that enables the next …
Santa Clara, California, United States
… the team and see how we can make a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue to rapidly grow the research and development of …
San Jose, California, United States +2 locations
Pay posted by employer$143,800–$230,000 per year
Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, …
San Jose, California, United States
Pay posted by employer$143,800–$230,000 USD per year
Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, …
Santa Clara, California, United States
NVIDIA is seeking a motivated and creative Senior Verification Engineer to join our Tegra SoC IP Verification team. Our mission is to build the IP that enables the next …
Santa Clara, California, United States +1 location
… interconnect/cache/core design is desirable. Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. Strong communication and interpersonal …
Santa Clara, California, United States
… never been a more exciting time to join our team! The NVIDIA VLSI team is looking for a Cell Modeling and Verification Engineer with strong experience in hardware design and methodologies to help develop NVIDIA's ground …
USA - El Segundo, CA
Pay posted by employer$98,600–$133,400
… and ECO implementation Ensure clean netlist handoffs and predictable convergence by partnering with RTL, verification, DFT, and backend partner companies Support chip‑level integration, top‑level timing closure, signoff …
Bengaluru, Karnataka, India +1 location
… integration with the testability features coordinated in the RTL. * Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation …
USA-Mendota Heights-Northland
Pay posted by employer$109,700–$175,500 USD per year
Senior Digital / Mixed-Signal IC Design or Verification Engineer Location: Mendota Heights, MN or Broomfield, CO Job Description Summary Join Broadcom, a global …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
