635 matching jobs for “ASIC Design Engineer”

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Nvidia

Senior Physical Design and Timing Engineer

Westford, Massachusetts, United States

… the team and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the …

Added Oct 27, 2026

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Nvidia

Lead Hardware Design Validation Engineer - Memory Subsystem

Santa Clara, California, United States

… and failure analysis for NVIDIA’s datacenter and graphics products. Drive review of memory partner’s design limits and test methodology. Integrate learnings into unique characterization and test plans for each …

Added Oct 31, 2026

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Intel

Senior Design Verification Engineer - Neuromorphic Computing

Hillsboro, Oregon, United States +4 locations

Full time
Regular

Pay posted by employer$122,440–$232,190 USD per year

… that ensure correctness at the lowest levels of hardware implementation. Working closely with architecture, design, and software teams, you will help drive verification strategies that enable first-pass silicon success. An …

Added Oct 27, 2026

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Nvidia

Senior Design Verification Engineer - GPU Memory Subsystem

Durham, North Carolina, United States

… team and see how you can make a lasting impact on the world. We're looking for a talented, motivated Senior Design Verification Engineer to join our GPU memory subsystem team in Durham, NC. Looking to join a dynamic team …

Added Oct 27, 2026

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Nvidia

Senior Logic Design Engineer, Cache Coherent Interconnects

Santa Clara, California, United States +1 location

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip …

Added Oct 31, 2026

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Cisco Systems

Physical Design Manager

Caesarea, Israel +1 location

Cisco Silicon One is seeking a Physical Design Manager. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire backend …

Added Oct 27, 2026

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Cisco Systems

ASIC High Speed AMS Technical Leader

Carlsbad, California, United States +1 location

Pay posted by employer$192,400–$275,800

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

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Marvell Technology

Physical Design Intern

Córdoba, Cordoba, Argentina

Part time
Internship

… • How is this technology used in the world that most people would recognize? What You Can Expect The engineer will implement tool flows, develop and define CAD methodologies, and generate scripts. He or she will …

Added Nov 3, 2026

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Northrop Grumman

FPGA Design Engineer Level 3/4 - Linthicum

United States-Maryland-Linthicum

Pay posted by employer$119,600–$179,400

… logic designs for space applications such as satellite command and control and sensor data processing Design, development, creation and modification of digital logic designs implemented with Xilinx and Microsemi FPGA …

Added Nov 3, 2026

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Marvell Technology

Package Layout Design Staff/Senior Staff Engineer

Bengaluru, Karnataka, India

Regular

… You Can Expect Marvell’s Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic packages. The engineer will be responsible for …

Added Nov 3, 2026

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Cisco Systems

ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs | 8-12 Years | Pune/ Bangalore)

Pune, Maharashtra, India +1 location

The Digital Design Lead for the Client Optics Group (COG) provides essential technical leadership in the development of …

Added Oct 27, 2026

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Analog Devices

Director, Digital Design

Bengaluru, Karnataka, India

& Responsibilities Responsibility to oversee local and remote digital design activities for 1 or more products which may include the technical leadership of silicon development. …

Added Nov 3, 2026

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Cisco Systems

ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Experience - 4 to 8 years

Bengaluru, Karnataka, India +1 location

… for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and …

Added Oct 27, 2026

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Cisco Systems

High-Speed SerDes Design Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$171,600–$245,000

… You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia …

Added Oct 27, 2026

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Marvell Technology

Physical Design Engineer Intern, MS - Summer 2027

Santa Clara, California, United States +6 locations

Internship

… fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell’s Physical Design teams span across multiple domains, giving you the opportunity to work on technologies that power …

Added Nov 3, 2026

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Marvell Technology

Physical Design Engineer Intern, BS - Summer 2027

Santa Clara, California, United States +6 locations

Internship

Added Nov 3, 2026

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Hewlett Packard Enterprise

Design Verification Manager

Sunnyvale, California, United States

Pay posted by employer$174,000–$352,500 USD per year

We are seeking a visionary and technically rigorous Design Verification Manager to lead our world-class silicon verification team. In this pivotal leadership role, …

Added Nov 3, 2026

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Cisco Systems

Hardware Design Engineer System Lead / SI/ System Architecture

Milpitas, California, United States

Pay posted by employer$194,600–$285,700

… and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our …

Added Oct 27, 2026

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Cisco Systems

System Architecture Engineer Leader (Hardware Board Design) (Onsite)

Milpitas, California, United States

Pay posted by employer$194,600–$285,700

Added Oct 27, 2026

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Cisco Systems

Senior Physical Design CAD

Caesarea, Israel +1 location

Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One …

Added Oct 27, 2026

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Cisco Systems

ASIC High Speed AMS Technical Leader

Carlsbad, California, United States +1 more

Pay posted by employer$192,400–$275,800

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Minimum Qualifications · employer excerpt

Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of high-speed AMS design experience
Demonstrated expertise in high-speed optical transceiver design (modulator drivers, TIA, CDR, PLLs, ADC/DAC) and proficiency with industry standard tools (Cadence Virtuoso, Spectre, Caliber, SystemVerilog, Verilog-AMS)
Demonstrated ability to lead design teams through full tapeout cycle, making critical decisions with limited data and delivering successful silicon products
Proficiency in Python or C for design automation, scripting, and analytical tools

About this opportunity

Original employer description

The application window is expected to close on: 01/18/2027

Meet the Team

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

Build the optical backbone of the AI revolution. As our High-Speed Analog/Mixed-Signal Design Engineer, you will directly lead the electrical specifications, custom circuit design, and verification strategies for Cisco’s next-generation 800G, 1.6T, and beyond silicon photonics modules.

Operating within our best-in-class Silicon Photonics team, you will own the end-to-end development cycle for 100G/200G/400G per Lambda driver integrated circuits that seamlessly integrate with Cisco's core routing, switching, and datacenter platforms.

Your technical leadership will span critical execution phases from concept to production:

Datapath & Control Ownership: Author high-performance mixed-signal datapath and low-speed control circuits for both receive and transmit paths—including photonic modulator drivers, serializers, PLLs, and TIAs—while rigorously optimizing for power, performance, testability, and cost.
Full-Chip Architecture & Integration: Drive full-chip electrical specifications and comprehensive verification test plans, coordinating tightly across electrical, optical, and product architecture teams.
Bring-Up & Yield Enhancement: Debug complex silicon and system-level bottlenecks hands-on during lab validation and bring-up phases to drive yield enhancements and failure analysis.
Technical Leadership & Mentoring: Guide and mentor analog, digital, and validation engineers, elevating our team’s engineering excellence across next-gen data center architectures.

Minimum Qualifications

Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of high-speed AMS design experience
Demonstrated expertise in high-speed optical transceiver design (modulator drivers, TIA, CDR, PLLs, ADC/DAC) and proficiency with industry standard tools (Cadence Virtuoso, Spectre, Caliber, SystemVerilog, Verilog-AMS)
Demonstrated ability to lead design teams through full tapeout cycle, making critical decisions with limited data and delivering successful silicon products
Proficiency in Python or C for design automation, scripting, and analytical tools

Preferred Qualifications

10-15 years of analog/mixed signal circuit design experience
Experience with silicon photonics driver ICs and direct-detect optical module architectures
Strong understanding of silicon photonics, optical subsystems, MSA standards (QSFP/QSFP-DD), and IEEE 802.3 specifications
Expertise in multiple high-speed PHYs, protocols and subsystems (SerDes 112Gbps/224Gbps PAM4, Ethernet, UCIE, clock and data recovery systems, PLLs, ADC/DAC circuits)
Demonstrated experience in design for testability (DFT) and test methodology development for large mixed-signal designs
Proven experience with lab instrumentation (digital communication analyzers, real-time scopes, BERTs), SI/PI and test fixture/PCB
Familiarity with optical sub-component models (photodiodes, modulators) and Verilog-A modeling for AMS simulations
Strong collaborator and teammate with the ability to work across teams in multiple sites

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $192,400.00 to $275,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$214,100.00 - $356,300.00

Non-Metro New York state & Washington state:

$192,400.00 - $317,200.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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