119 matching jobs for “Senior DFT Engineer”

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Intel

Senior Technical Lead - CPU Physical Design

Bengaluru, Karnataka, India

We are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from …

Added Oct 27, 2026

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Jabil

Principal Engineer Medium Voltage Electrical

Prince George, VA

… UL requirements where applicable, utility requirements, and customer-specific specifications. Serve as the senior MV electrical engineering representative for customer technical reviews, architecture discussions, issue …

Added Oct 28, 2026

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Intel

Sr Staff Substrate Yield Lead

Phoenix, Arizona, United States

Pay posted by employer$180,770–$255,200 USD per year

Intel Corporation is seeking a high-impact Yield Development Engineer to drive yield performance for cutting-edge manufacturing processes within the Substrate Technology and …

Added Oct 27, 2026

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Nvidia

Senior Technical Program Manager – DFX Software Methodology

Santa Clara, California, United States

NVIDIA is now looking for a Senior Technical Program Manager to join our DFX engineering team and lead the software methodology programs that …

Added Oct 27, 2026

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RTX

Principal Engineer Materials Modeling (Remote)

East Hartford, Connecticut, United States

… Materials and Process Engineering (MPE) organization in East Hartford, CT is looking for a highly motivated Senior Principal Engineer- Materials and Process Modeling who can support the development and implementation of …

Added Oct 27, 2026

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KLA

Embedded Software Engineer (C/C++ | Micro Controller)

Milpitas, California, United States

Full time
Regular

Pay posted by employer$136,300–$231,700 per year

… the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. The Surfscan group includes a team of engineers, technology …

Added Oct 15, 2026

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General Motors

Staff Hardware Engineer – DFx (Manufacturing, Test & Tooling)

Warren, Michigan, United States +1 location

Hybrid
Full time
Regular

… electrification, central compute, and autonomous technologies. We are building a high-energy team of Senior DFx (Design for Manufacturing, Test, and Tooling) engineers to serve as the critical link between internal …

Added Oct 12, 2026

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Cisco Systems

ASIC Engineering Technical Leader

Bengaluru, Karnataka, India

… highly complex ASICs and SoCs. You will own the end-to-end test development lifecycle from pre-silicon DFT engagement to post-silicon bring-up and high-volume manufacturing (HVM) release. As a senior technical …

Added Oct 27, 2026

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Nvidia

Principal Solutions Architect – Semiconductor Test

Santa Clara, California, United States

… strategy for semiconductor test. This covers wafer and package test operations from start to finish. This senior individual contributor role is central to our manufacturing and product engineering teams. You will lead …

Added Oct 31, 2026

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Intel

Product Development/DFX Lead - Neuromorphic Computing

Hillsboro, Oregon, United States +4 locations

Pay posted by employer$141,910–$269,100 USD per year

… technology with the versatility demanded by modern AI workloads. Position Overview We are seeking a senior product development engineer to lead the DFT/DFX strategy for Intel's neuromorphic silicon program. This …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs | 8-12 Years | Pune/ Bangalore)

Pune, Maharashtra, India +1 location

… expertise in high-speed optical interconnects and mastery of the complete ASIC/SoC design flow, including DFT, physical design, and verification. Furthermore, the position requires the ability to drive technical …

Added Oct 27, 2026

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Nvidia

EDA Methodology Architect

Santa Clara, California, United States +1 location

… in parallel computing, machine learning, and specialized algorithms for VLSI design. We are seeking a Senior P&R Methodology Architect to define and own the next generation RTL2GDS flow for advanced nodes (3nm and …

Added Oct 31, 2026

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Cisco Systems

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Pune, Maharashtra, India

… including AI/ML workloads, and next-generation data center architectures. Your Impact As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you …

Added Oct 27, 2026

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Nvidia

Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes

Santa Clara, California, United States

Are you looking for a Digital Design Manager role? As a Senior Digital Design Manager in our Mixed-Signal High-Speed I/O SerDes group, you'll lead a team working on …

Added Oct 31, 2026

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Intel

CPU RTL Design Manager

Bengaluru, Karnataka, India

… Cross-Functional Collaboration - Partner with Architecture, Design, Validation, Physical Design, DFT, Power, Security, and Product Engineering teams. Influence technical decisions across multiple …

Added Oct 27, 2026

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Cisco Systems

Leader, Semiconductor Product Engineering

San Jose, California, United States +3 locations

Pay posted by employer$194,600–$285,700

… (HVM) Collaborate with design & test teams to establish manufacturing and test strategies, including DFT implementation, test hardware specs, and test program creation Deliver AI-Driven process transformation to …

Added Oct 27, 2026

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GE Aerospace

Test Systems Technical Lead

Cheltenham, England, United Kingdom

Full time
Regular

… system architectures and strategies are aligned to the overall product architecture. Engage SMEs and Chief Engineer’s Office as needed to resolve complex technical issues, de-risk solutions, and ensure compliance with …

Added Oct 27, 2026

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RTX

Associate Director - Technical

IN-KA-BENGALURU-NORTHGATE ~ Sy No 2/2 Venkatala Village ~ SY NO 2/2 VENKATALA VILLAGE, Yelahanka Hobli

… EMC/EMI, safety, reliability, and derating across programs. • Provide technical direction and mentorship to senior engineers and specialists in power electronics, motor control, and embedded systems, ensuring rigorous …

Added Oct 27, 2026

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Technical Program Manager

Maplewood, Minnesota, United States +1 location

Remote

Pay posted by employer$250,253–$305,864

… Design for Excellence (DFx) principles, including Design for Manufacturability (DFM) and Design for Test (DFT). Experience with statistical process control (SPC), process capability analysis (Cpk/Ppk), and yield …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Pune, Maharashtra, India

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Minimum Qualifications · employer excerpt

Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
8-12 years of functional verification experience
Strong skills in SystemVerilog, Python, C and UVM methodology
Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols

4 more in the full description below.

About this opportunity

Original employer description

Meet the Team

Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.

You will work with Cisco's outstanding Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.

Your Impact

As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you will create verification documentation and work with senior engineers to help with defining the verification methodology and developing testbench components. During the initial design phase, you will be a part of block level verification and then you will transition to full chip verification. You will run verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions. You will develop functional coverage models, assertions, and debug complex verification issues within a UVM-based framework. Prior to tapeout you will run functional scenarios with CPU FW loaded and verify functionality at the CPU sub-system level. You may be involved in FPGA verification. Post Silicon you will be involved in ATE test plan and test vector generation, ATE testing and release to production.

Develop testbench components for Silicon Photonics subsystems. Proven ability to build UVM components (agents, drivers, monitors, scoreboards, sequences) and implement constrained-random and directed test strategies
Ability to understand coverage metrics and functional specifications
Understand and implement verification scenarios per full chip analog and digital verification test plans
Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs
FW/C-Coding and verification of CPU sub-systems with FW
Must have good knowledge of Python and C. Develop scripts for automated analysis and reports
Good understanding of RTL digital design and DFT (Design for Test) principles
Excellent organizational, teamwork, and communication skills

Minimum Qualifications

Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
8-12 years of functional verification experience
Strong skills in SystemVerilog, Python, C and UVM methodology
Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow
You must be a team player and be able to drive decisions quickly with consensus building.
Strong analytical, problem-solving and debugging skills
Strong teamwork, communication, and organizational skills

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

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