332 matching jobs for “SoC Design Verification Engineer”

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Nvidia

Senior Mixed-Signal Design Engineer

Santa Clara, California, United States

We are looking for an Engineer to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the …

Added Oct 31, 2026

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Intel

IP RTL Senior Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

The Role and Impact: As an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified …

Added Oct 27, 2026

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Intel

GPU Senior Logic Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

GPU Senior Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation …

Added Oct 27, 2026

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Analog Devices

Principal Engineer, Digital Design Engineering

Bengaluru, Karnataka, India

As an SoC Chip Lead, you will lead SoC execution from spec to silicon across domains. You will be responsible to …

Added Nov 3, 2026

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Intel

Chassis IP Senior Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

Intel is seeking an experienced Logic Design engineer for the Intel Chassis Group, which is chartered to deliver the chassis for SoCs within Intel. The …

Added Oct 27, 2026

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Analog Devices

Staff Engineer, Digital Design Engineering

Bengaluru, Karnataka, India

… stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X . Staff Digital Design Engineer Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, …

Added Nov 3, 2026

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Analog Devices

Staff Mixed-Signal Design Engineer

Newbury, England, United Kingdom +4 locations

As a Staff Mixed Signal Design Engineer, you will provide technical leadership in the design and development of sophisticated mixed-signal …

Added Nov 3, 2026

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Analog Devices

Senior Engineer, Digital Design (Physical)

Wilmington, Massachusetts, United States

Pay posted by employer$116,960–$160,820

… day-to-day block ownership. Key Responsibilities • Methodology Leadership: Drive improvements to physical design methodology, with a focus on flow standardization, reuse, execution efficiency, and more predictable design …

Added Nov 3, 2026

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Marvell Technology

Sr. Staff Engineer, Physical Design

Da Nang, Da Nang City, Vietnam

Full time
Regular

… trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Central Engineering ASIC Design Services Team within Marvell provides chip solutions for next generation 5G carriers, cloud data centers, …

Added Nov 3, 2026

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Intel

Senior GPU Physical Design Engineer

Folsom, California, United States +2 locations

Full time
Regular

Pay posted by employer$164,470–$232,190 USD per year

… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Pune, Maharashtra, India

… transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy …

Added Oct 27, 2026

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Nvidia

ASIC Design Engineer – Clocks IP

Santa Clara, California, United States +1 location

The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …

Added Oct 27, 2026

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Marvell Technology

Senior Staff Digital Design Engineer

Irvine, California, United States

Full time
Regular

… Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Digital ASIC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the high …

Added Nov 3, 2026

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Intel

CPU Senior Clock Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

The Role and Impact Join a Team That Defines the Heartbeat of Next-Generation CPUs. As a CPU Senior Clock Design Engineer, you will contribute to the design, implementation, analysis, and optimization of clock …

Added Oct 27, 2026

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Broadcom

R&D Engineer IC Design

Bengaluru, Karnataka, India

Full time
Regular

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test …

Added Nov 3, 2026

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Broadcom

R&D Engineer IC Design

Bengaluru, Karnataka, India

Full time
Regular

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test …

Added Nov 3, 2026

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Broadcom

R&D Engineer IC Design

Bengaluru, Karnataka, India

Full time
Regular

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test …

Added Nov 3, 2026

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Intel

Mixed Signal Logic Design Engineer

Malaysia, Penang

Full time
Regular

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or high-speed IPs required to …

Added Oct 27, 2026

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Marvell Technology

Principal, IC Digital Design Engineer

Irvine, California, United States

Full time
Regular

… trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal, Digital IC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the high …

Added Nov 3, 2026

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Nvidia

Senior ASIC Design Engineer - Memory Subsystem

Santa Clara, California, United States

… join the team and see how we can make a lasting impact on the world. NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem Team! What you'll be doing : As a member of our Memory Subsystem …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Pune, Maharashtra, India

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Minimum Qualifications · employer excerpt

Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
8-12 years of functional verification experience
Strong skills in SystemVerilog, Python, C and UVM methodology
Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols

4 more in the full description below.

About this opportunity

Original employer description

Meet the Team

Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.

You will work with Cisco's outstanding Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.

Your Impact

As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you will create verification documentation and work with senior engineers to help with defining the verification methodology and developing testbench components. During the initial design phase, you will be a part of block level verification and then you will transition to full chip verification. You will run verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions. You will develop functional coverage models, assertions, and debug complex verification issues within a UVM-based framework. Prior to tapeout you will run functional scenarios with CPU FW loaded and verify functionality at the CPU sub-system level. You may be involved in FPGA verification. Post Silicon you will be involved in ATE test plan and test vector generation, ATE testing and release to production.

Develop testbench components for Silicon Photonics subsystems. Proven ability to build UVM components (agents, drivers, monitors, scoreboards, sequences) and implement constrained-random and directed test strategies
Ability to understand coverage metrics and functional specifications
Understand and implement verification scenarios per full chip analog and digital verification test plans
Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs
FW/C-Coding and verification of CPU sub-systems with FW
Must have good knowledge of Python and C. Develop scripts for automated analysis and reports
Good understanding of RTL digital design and DFT (Design for Test) principles
Excellent organizational, teamwork, and communication skills

Minimum Qualifications

Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
8-12 years of functional verification experience
Strong skills in SystemVerilog, Python, C and UVM methodology
Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow
You must be a team player and be able to drive decisions quickly with consensus building.
Strong analytical, problem-solving and debugging skills
Strong teamwork, communication, and organizational skills

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

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