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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
Santa Clara, California, United States +4 locations
Pay posted by employer$220,920–$311,890 USD per year
… deliver power, performance, and scalability across future nodes and products. We're looking for a Principal Engineer who thrives on solving hard problems, someone who can bring deep circuit expertise and help define the …
Somerset, New Jersey, United States +1 location
Pay posted by employer$116,960–$160,820
As a Senior Physical Design Engineer, you will play a key role in the implementation and delivery of complex digital and mixed-signal …
Bengaluru, Karnataka, India
… company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of …
Hillsboro, Oregon, United States
Pay posted by employer$122,440–$172,860 USD per year
… leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for …
Malaysia, Penang +1 location
The Role and Impact As an E-Core (Atom) CPU Layout Design Engineer, you will play a pivotal role in shaping the physical layout of Intel's cutting-edge Atom …
USA - Huntsville, AL
Pay posted by employer$112,200–$151,800
Design high speed digital circuits and perform signal integrity analysis Focus on electronic systems and …
Malaysia, Penang
… CPU products. Whether you're a college graduate eager to launch your career or an experienced engineer ready to solve some of the industry's most complex technical challenges, you'll have the opportunity to …
Santa Clara, California, United States +1 location
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …
Santa Clara, California, United States +2 locations
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement the world's leading SoC's and GPU's. …
United States-Illinois-Rolling Meadows
Pay posted by employer$119,600–$179,400
… Space Systems today! Our team is chartered with providing the skills, innovative technologies to develop, design, produce and sustain optimized product lines across the sector while providing a decisive advantage to the …
China, Beijing, Haidian, Xixiaokou
Technical Leadership Lead block-level and chip-level digital architecture definition, RTL design, and implementation for digital SoCs. Drive key architecture and micro-architecture decisions, balancing …
Guadalajara, Jalisco, Mexico
As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring …
Wilmington, Massachusetts, United States
Pay posted by employer$157,080–$227,460
carries both hands-on design ownership and technical leadership of junior and senior engineers. This is a hands-on technical leadership …
Bengaluru, Karnataka, India +1 location
… work. Come join the team and see how you can make a lasting impact on the world. We are now looking for RTL Design engineers for our BOOT and Power management Subsystem Design deployed in Automotive and Client chips. As …
Santa Clara, California, United States
NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have …
Santa Clara, California, United States
… people in the world and there has never been a more exciting time to join our team! We are seeking an ASIC Design Engineer - New College Graduate to implement the world’s leading SoC's and GPU's. This position offers the …
USA - El Segundo, CA +1 location
Pay posted by employer$146,200–$197,800
ASIC / FPGA Digital Design Engineer – (Lead or Senior) Company: Boeing Space, Intelligence & Weapons Systems has an exciting …
Malaysia, Penang +1 location
The Role and Impact: As an E-Core (Atom) CPU Layout Design Engineer, you will play a pivotal role in shaping the physical layout of Intel's cutting-edge Atom …
Guadalajara, Jalisco, Mexico
The Role and Impact As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring …
Guadalajara, Jalisco, Mexico
As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
