279 matching jobs for “Senior ASIC Design Engineer”

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Northrop Grumman

Principal/ Sr. Principal FPGA Design Engineer

United States-Illinois-Rolling Meadows

Pay posted by employer$119,600–$179,400

… Space Systems today! Our team is chartered with providing the skills, innovative technologies to develop, design, produce and sustain optimized product lines across the sector while providing a decisive advantage to the …

Added Nov 3, 2026

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Boeing

ASIC Subsystem Engineer (Mid-level or Lead)

USA - El Segundo, CA

In person

Pay posted by employer$119,850–$162,150

Define, develop and validate next-generation multi-ASIC architectures incorporating digital signal-processing cores for digital communication subsystems. …

Added Oct 12, 2026

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Analog Devices

Senior MEMS Design and Simulation Engineer

Wilmington, Massachusetts, United States

Pay posted by employer$110,385–$151,808

Analog Devices, Inc. currently has a position open for a Senior MEMS Design and Simulation Engineer within the Advanced MEMS Development group under the Aerospace, …

Added Nov 3, 2026

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Nvidia

Senior Physical Design and Timing Engineer

Westford, Massachusetts, United States

… join the team and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the …

Added Oct 27, 2026

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Cisco Systems

Senior Hardware Board Design Engineer - High-Speed

Milpitas, California, United States

Pay posted by employer$154,900–$225,300

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to product ion—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

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Broadcom

Senior Serdes System Design Engineer/Architect

Austin, Texas, United States +2 locations

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will …

Added Oct 5, 2026

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Broadcom

Senior Serdes System Design Engineer/Architect

Austin, Texas, United States +2 locations

Full time
Regular

Pay posted by employer$121,900–$195,000 USD per year

This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will …

Added Oct 5, 2026

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Nvidia

Senior Design Verification Engineer - GPU Memory Subsystem

Durham, North Carolina, United States

… the team and see how you can make a lasting impact on the world. We're looking for a talented, motivated Senior Design Verification Engineer to join our GPU memory subsystem team in Durham, NC. Looking to join a dynamic …

Added Oct 27, 2026

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Intel

Senior Design Verification Engineer - Neuromorphic Computing

Hillsboro, Oregon, United States +4 locations

Full time
Regular

Pay posted by employer$122,440–$232,190 USD per year

… that ensure correctness at the lowest levels of hardware implementation. Working closely with architecture, design, and software teams, you will help drive verification strategies that enable first-pass silicon success. An …

Added Oct 27, 2026

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Nvidia

CPU Design Methodology Engineer

Hillsboro, Oregon, United States +3 locations

We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineering Technical Leader

Bengaluru, Karnataka, India

… from pre-silicon DFT engagement to post-silicon bring-up and high-volume manufacturing (HVM) release. As a senior technical driver, your responsibilities will include: • Test Architecture & Development: Architect, write, …

Added Oct 27, 2026

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Nvidia

Senior Logic Design Engineer, Cache Coherent Interconnects

Santa Clara, California, United States +1 location

We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of …

Added Oct 31, 2026

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Micron Technology

Manager, ASIC DV

Hyderabad - Phoenix Aquila, India

… towards Efficient, Scalable IP/SS Verification Environment and Methodologies Interact with Architecture and Design Team to establish standard flows and Deliverables alignments. Understanding to Architecture requirements …

Added Nov 3, 2026

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Cisco Systems

Senior Physical Design CAD

Caesarea, Israel +1 location

Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One …

Added Oct 27, 2026

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Leidos Holdings

Principal Hardware Design Engineer

Laurel, Maryland, United States

Pay posted by employer$131,300–$237,350

… national security challenges. About the Opportunity Leidos is seeking an accomplished Principal Hardware Design Engineer to provide technical leadership in the design, development, testing, and reverse engineering of …

Added Nov 3, 2026

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Marvell Technology

Package Layout Design Staff/Senior Staff Engineer

Bengaluru, Karnataka, India

Regular

… You Can Expect Marvell’s Central Engineering team is seeking a talented High-speed IC package development engineer to contribute to the development of advanced microelectronic packages. The engineer will be responsible for …

Added Nov 3, 2026

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Marvell Technology

Principal Engineer, Physical Design

Hsinchu City

Full time
Regular

… and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure …

Added Nov 3, 2026

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Marvell Technology

Senior Staff Manager, Physical Design

Hsinchu City

Full time
Regular

Marvell is seeking a Senior Manager of Physical Design to lead project-level physical design execution and support team growth at the …

Added Nov 3, 2026

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Cisco Systems

IC Package Design Engineer

San Jose, California, United States

Pay posted by employer$155,000–$222,600

• Contribute to package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed …

Added Oct 27, 2026

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GE Aerospace

Staff Engineer - FPGA Design/Verification

Grand Rapids, Michigan, United States +2 locations

Full time
Regular

Summary GE Aerospace is seeking an experienced Staff Engineer – FPGA Design/Verification to lead the development of custom logic for advanced avionics hardware. This …

Added Oct 27, 2026

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Northrop Grumman

Principal/ Sr. Principal FPGA Design Engineer

United States-Illinois-Rolling Meadows

Pay posted by employer$119,600–$179,400

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Basic Qualifications · employer excerpt

Principal FPGA Design Engineer (Level 3): Bachelors’ degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 5 years (or MS and 3+ years, or a PhD) of FPGA/ASIC design experience.
Sr. Principal FPGA Design Engineer (Level 4): Bachelors’ degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 8 years (or MS and 6+ years, or PhD +3 years) of FPGA/ASIC design experience.
In-depth knowledge of VHDL and/or Verilog
-Proficiency in High level synthesis (Xilinx Vivado HLS AND/OR Mentor Catapult HLS) with C++
Expertise achieving timing closure on dense FPGA designs

8 more in the full description below.

About this opportunity

Original employer description

RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE REQUIRED FOR START: No

CLEARANCE TYPE: None

TRAVEL: Yes, 10% of the Time

Description

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

Embark on a career putting innovative, reliable, and agile products and ideas into orbit, and beyond. Northrop Grumman Space Systems has opportunities waiting for you that play a vital role in human space exploration, national defense, and scientific discovery, supporting multiple programs across the universe. With us, you’ll discover a culture of curiosity and collaboration that will have you Defining Possible from the day you start. Our space systems connect and protect millions of people on earth every day, now and for the future. Explore your future and launch your career with Northrop Grumman Space Systems today!

Our team is chartered with providing the skills, innovative technologies to develop, design, produce and sustain optimized product lines across the sector while providing a decisive advantage to the warfighter. Come be a part of our mission!

We are seeking a talented FPGA Design engineer with signal processing experience to join our growing team in Rolling Meadows, IL.

As an FPGA Design Engineer, you will join our diverse team and be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and place & route for our digital signal processing products. You will be working with digital subsystem and circuit card designs that utilize the latest FPGA technologies from all major vendors and device families including Xilinx, Intel (Altera), and Microsemi (Actel) and support high speed interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Your expertise in digital signal processing, modeling and simulation, and circuit level design and test are desired for this position.

This position will be filled as a level 3 or level 4.

Basic Qualifications

Principal FPGA Design Engineer (Level 3): Bachelors’ degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 5 years (or MS and 3+ years, or a PhD) of FPGA/ASIC design experience.
Sr. Principal FPGA Design Engineer (Level 4): Bachelors’ degree in Electrical Engineering, Computer Engineering or similar engineering discipline with a minimum 8 years (or MS and 6+ years, or PhD +3 years) of FPGA/ASIC design experience.
In-depth knowledge of VHDL and/or Verilog
-Proficiency in High level synthesis (Xilinx Vivado HLS AND/OR Mentor Catapult HLS) with C++
Expertise achieving timing closure on dense FPGA designs
Working knowledge of DSP structures and techniques
Proficient in Python, C or other scripting languages
Extensive experience generating test benches
Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis
Experience with FPGA simulation tools to verify performance of complex RTL blocks
Experience with Xilinx or Intel/Altera FPGA architectures and design tools
Soft skills to include: Adaptive, creative, collaborative, comfortable working independently, enjoys solving difficult problems while communicating with all levels of an organization internally and externally
Must be a US Citizen with ability to obtain and maintain Top Secret security clearance with SCI

Preferred Qualifications:

Current or Active Top Secret with SCI/SAP security clearance
Extensive experience implementing Digital Signal or Image Processing algorithms on FPGAs
Extensive experience with high-speed interfaces: Ex. AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet, etc.
Working knowledge of SDR platforms and architectures
Extensive experience developing FPGA algorithms for SoC based architectures
Experience developing FPGA/SW interfaces and controls
Experience developing and prototyping in MATLAB/Simulink
Experience debugging down to the hardware level & experience using Signal Generators, Logic Analyzers, Digital Oscilloscopes and Embedded FPGA
Debugging tools.
Experience and knowledge developing requirements for FPGA-based products
Experience with Electronic Design Automation (EDA) Tools: Mentor Graphics ModelSim/QuestaSim, Synplify, Xilinx ISE/ Vivado, Intel Quartus, Altera SOPC Builder, Altera Qsys, DSP Builder.
Experience working with or developing test benches using SystemVerilog and Universal Verification Methodology (UVM)
-Familiarity with revision control, documentation, planning, and review systems similar to GIT/SVN/ClearCase, DOORS, Jira/Rally/ClearQuest

Curious about all the exciting developments with the Northrop Grumman Space Sector? Click the link below:

https://www.northropgrumman.com/space

Working at Northrop Grumman is more than just a paycheck. We offer a comprehensive Total Rewards and benefits package designed to help you thrive at work and in life. For more information on our Total Rewards package, please visit our Total Rewards site.

Northrop Grumman Total Rewards

#SpaceEngJobs
#SpaceSoftwareJobs

#SPEnhancedERAP

#RollingMdwSpace

Primary Level Salary Range: $119,600.00 - $179,400.00

Secondary Level Salary Range: $149,300.00 - $223,900.00

The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.

Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

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