344 matching jobs for “SoC Design Verification Engineer”

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Nvidia

Senior Digital Design Verification Engineer - Hardware

Santa Clara, California, United States

We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU …

Added Oct 31, 2026

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Nvidia

Senior ASIC Design Verification Engineer - LPU

Canada, Remote

… join the team and see how you can make a lasting impact on the world. NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the design and implementation of the world’s leading inference accelerator. This …

Added Oct 31, 2026

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Nvidia

Senior ASIC Design Verification Engineer - LPU

Santa Clara, California, United States +5 locations

Added Oct 27, 2026

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Intel

Senior Design Verification Engineer - Neuromorphic Computing

Hillsboro, Oregon, United States +4 locations

Full time
Regular

Pay posted by employer$122,440–$232,190 USD per year

… the versatility demanded by modern AI workloads. Position Overview We are seeking experienced pre-silicon verification engineers who are passionate about driving innovation at the intersection of advanced semiconductor …

Added Oct 27, 2026

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Cisco Systems

ASIC Design Verification Engineer, Technical Leader

San Jose, California, United States

Pay posted by employer$186,900–$267,700

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

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Analog Devices

Senior Manager, Design Verification Engineering

Bengaluru, Karnataka, India

Lead design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible …

Added Nov 3, 2026

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Boeing

Entry Level ASIC/FPGA Design Verification Engineer

USA - El Segundo, CA

In person
Full time
Regular

Pay posted by employer$79,050–$106,950

Execute assigned verification tasks and progressively increase ownership. Develop simulation, debug, coverage, and requirements …

Added Oct 14, 2026

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Broadcom

Verification Engineer

San Jose, California, United States

Pay posted by employer$129,400–$207,000 USD per year

… working on IPs for ASIC products such as custom AI chips. This position is responsible for IP and subsystem verification, including processor subsystem among many other IPs. Requirements: Experience in architecting modern …

Added Nov 12, 2026

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Intel

Staff SOC DFT Engineer

Malaysia, Penang

Full time
Regular

… and Impact Are you ready to make a significant contribution to cutting-edge semiconductor designs? As a DFT Design Engineer, you will play a critical role in shaping the testability, debuggability and reliability of …

Added Oct 27, 2026

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Nvidia

ASIC Design Verification Engineer - New College Grad 2026

Austin, Texas, United States

… world. This is our life’s work, to amplify human inventiveness and intelligence. The NVIDIA System-On-Chip (SOC) group is looking for an entry level ASIC Verification Engineer! In this position you will have the chance …

Added Oct 31, 2026

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Boeing

ASIC / FPGA Design Verification Engineer – (Lead or Senior)

USA - El Segundo, CA +1 location

Full time
Regular

Pay posted by employer$146,200–$197,800

, verification strategy influence, and leadership of verification efforts across complex programs. Overview Engineers …

Added Oct 12, 2026

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Boeing

ASIC / FPGA Design Verification Engineer - (Associate or Experienced)

USA - El Segundo, CA +1 location

Full time
Regular

Pay posted by employer$98,600–$133,400

ASIC / FPGA Design Verification Engineer - (Associate or Experienced) Company: Boeing Space, Intelligence & Weapons Systems …

Added Oct 12, 2026

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Intel

Sr Director, XSE Design Verification Engineering

Santa Clara, California, United States

Full time
Regular

Pay posted by employer$256,050–$361,480 USD per year

The Role and Impact As a Design Verification Engineering Manager, you will lead a dynamic team of design verification engineers responsible …

Added Oct 31, 2026

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Broadcom

PCIe Verification Engineer

Bengaluru, Karnataka, India 2 postings

PCIe Verification Engineer Seeking an experienced PCIe Verification Engineer to join Broadcom ASIC Product Division to be …

Added Nov 12, 2026

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Nvidia

Physical Verification Engineer

Israel, Tel Aviv +1 location

NVIDIA is seeking a Physical Verification Engineer to help ensure our ASIC and SoC designs are clean, correct, and ready for tapeout. This role …

Added Oct 27, 2026

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Nvidia

Formal Verification Engineer

China, Shanghai

The NVIDIA GPU clocks group is looking for excellent Senior Formal Verification engineers to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team …

Added Oct 27, 2026

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Nvidia

ASIC Verification Engineer

Santa Clara, California, United States

NVIDIA is seeking an outstanding ASIC Verification Engineer to verify the design and implementation of the world’s leading SoC's and GPU's. This position …

Added Oct 27, 2026

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Nvidia

Verification Engineer - PCIE

Bengaluru, Karnataka, India 3 postings

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the …

Added Oct 27, 2026

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Nvidia

Verification Engineer - PCIE

Bengaluru, Karnataka, India

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the …

Added Oct 27, 2026

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Nvidia

ASIC Verification Engineer

Santa Clara, California, United States

NVIDIA’s Clocks team is looking for an experienced ASIC Design Verification engineer to join our team! The NVIDIA Clocks Team is committed to deliver high-quality …

Added Oct 27, 2026

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Cisco Systems

ASIC Design Verification Engineer, Technical Leader

San Jose, California, United States

Pay posted by employer$186,900–$267,700

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Minimum Qualifications · employer excerpt

Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodology
Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC
Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
Prior experience with functional coverage and constrained random DV environments.
Scripting skills: Perl and/or Python scripting

About this opportunity

Original employer description

The application window is expected to close on: 11/18/2026

This role will work onsite out of our San Jose, CA office.

Meet The Team:

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.

Your Impact:

Maintaining existing DV environments and enhancing them
Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
Write test plan, develop test cases, debug regression failures and drive to module verification closure
Ensuring complete verification coverage through implementation and review of code and functional coverage
Use AI tools to develop innovative methods and processes to improve quality of design verification.

Minimum Qualifications:

Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodology
Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC
Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
Prior experience with functional coverage and constrained random DV environments.
Scripting skills: Perl and/or Python scripting

Preferred Qualifications:

Strong domain experience in one or more protocols is a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
Experience with Veloce/HAPS is a plus
Formal verification (iev/vc formal) knowledge is a plus

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$186,900.00 - $307,800.00

Non-Metro New York state & Washington state:

$166,300.00 - $274,100.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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