347 matching jobs for “ASIC Verification Engineer”

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Nvidia

Senior ASIC Design Engineer

US, CA, Santa Clara +1 location

We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. …

Added Oct 27, 2026

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Broadcom

Job Description: · Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. · Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for …

Added Oct 19, 2026

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Cisco Systems

Layout ASIC Engineer

Bengaluru, India

We are looking for a talented and motivated Layout Engineer to join Cisco’s Client Optics Group (COG) Engineering Team. In this role, you will support the physical …

Added Oct 27, 2026

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Senior ASIC Design Engineer

Vancouver, Washington, United States

Full time
Reg Employee

Pay posted by employer$116,150–$182,400 USD per year

Lead functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, verification, silicon validation, and qualification. Proactively work with other …

Added Oct 12, 2026

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Nvidia

Senior ASIC Design Engineer

US, CA, Santa Clara

will include architecture and micro-architecture design, RTL design and synthesis, and logic and timing verification using pioneering CAD tools and semiconductor process technologies. In addition to the design role, you will …

Added Oct 27, 2026

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Broadcom

IC Verification Engineer

San Jose, California, United States

Full time
Regular

Pay posted by employer$143,800–$230,000 USD per year

Responsibilities: Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies. Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these …

Added Oct 5, 2026

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Broadcom

ASIC Design Automation Engineer

Fort Collins, Colorado, United States

Full time
Regular

Pay posted by employer$129,400–$207,000 USD per year

Broadcom’s ASIC Products Division is seeking a Design Automation Software Development Engineer. They will define, develop, …

Added Oct 5, 2026

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Nvidia

Senior ASIC Design Engineer

US, CA, Santa Clara

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. …

Added Oct 27, 2026

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Nvidia

Senior Verification Engineer, SoC

US, CA, Santa Clara +4 locations

NVIDIA is seeking an exceptional Senior SoC ASIC Verification Engineer to confirm the functionality of the world’s most powerful AI-enabled SoCs. These SoCs power self-driving …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineer- CAD

San Jose, California, United States

Pay posted by employer$155,000–$222,600

… users. Support releases, tool qualification, and regression signoff. Collaborate with DFT Design, ATPG, Verification, Physical Design, and CAD teams. Minimum Qualifications: Bachelor’s degree in Electrical or Computer …

Added Oct 27, 2026

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Nvidia

ASIC Physical Design Engineer

China, Shanghai

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer

US, CA, Santa Clara +1 location

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the …

Added Oct 27, 2026

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Palo Alto Networks

Senior ASIC Design Engineer

Office - USA - CA - Headquarters

About the Role Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own …

Added Oct 27, 2026

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Palo Alto Networks

Senior ASIC Emulation Engineer

Office - USA - CA - Headquarters

Your Career As a Senior/Lead ASIC Emulation Engineer on the ASIC team, you will drive the execution, verification, and validation of …

Added Oct 27, 2026

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Cisco Systems

ASIC Physical Design Engineer

Caesarea, Israel

Cisco Silicon One is seeking a Physical Design Engineer. Meet the Team The Physical Design team within Cisco Silicon One owns backend methodology and flow …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC Layout Engineer

Armenia

We are hiring an ASIC Engineer to own standard cell layout for our next-generation ASICs on innovative FinFET and GAA nodes. You …

Added Oct 28, 2026

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Broadcom

Principal Physical Verification Engineer

San Jose, California, United States

Pay posted by employer$143,800–$230,000 USD per year

Principal Physical Design Engineer — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — Physical Design …

Added Oct 25, 2026

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Cisco Systems

ASIC Physical Design Engineer

Armenia

… and routing. Optimize power, performance, and area while maintaining design correctness through formal verification. Execute static timing analysis, physical verification, formal checks, and signoff closure to ensure …

Added Oct 27, 2026

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Nvidia

Senior Physical Verification Engineer

Israel, Tel Aviv +1 location

… debug, and the ability to scale best practices across multiple programs. This is a great match for an engineer who wants to combine technical depth with broad project impact. What you’ll be doing: Own physical …

Added Oct 27, 2026

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Boeing

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$98,600–$133,400

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead) Company: …

Added Oct 12, 2026

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Cisco Systems

ASIC Physical Design Engineer

Caesarea, Israel

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Minimum Qualifications · employer excerpt

B.Sc. or M.Sc. in Electrical Engineering or a related field.
2+ years of hands-on experience in VLSI backend design or a relevant physical design domain.
Strong understanding of the Place & Route flow.
Hands-on experience with physical synthesis, place and route, optimization, timing closure, or design floor planning.

About this opportunity

Original employer description

Cisco Silicon One is seeking a Physical Design Engineer.

Meet the Team

The Physical Design team within Cisco Silicon One owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of Cisco's most advanced silicon products.

We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon.

Your Impact

You will be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS.

You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs.
Support design floor planning and implementation planning in collaboration with senior physical design engineers.
Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure.
Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff.
Partner with cross-functional teams to debug implementation issues and improve backend flow quality.

Minimum Qualifications:

B.Sc. or M.Sc. in Electrical Engineering or a related field.
2+ years of hands-on experience in VLSI backend design or a relevant physical design domain.
Strong understanding of the Place & Route flow.
Hands-on experience with physical synthesis, place and route, optimization, timing closure, or design floor planning.

Preferred Qualifications:

Understanding of physical construction and integration concepts across backend implementation.
Knowledge of physical design verification methodology, including LVS and DRC.
Familiarity with physical design EDA tools such as Synopsys, Cadence, or similar platforms.
Ability to learn independently, take ownership of assigned tasks, and work effectively with teammates.
Strong problem-solving skills and attention to detail in complex technical environments.

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Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

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