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Santa Clara, California, United States +1 location
… and thermal challenges. Analyze peak current, Di/Dt, IR and EM requirements, and collaborate closely with ASIC designers, Power Integrity, Packaging experts and Product engineers to understand challenges and formulate …
… technical program management, test engineering, DFX or post-silicon validation Hands-on knowledge of the ASIC/SoC development flow, with working familiarity with DFX concepts (SCAN, ATPG, MBIST, JTAG) and post-silicon …
Santa Clara, California, United States +3 locations
Full time
Regular
Pay posted by employer$220,920–$311,890 USD per year
The Role and Impact As a SoC Cache Design Engineer, you will play a pivotal role in developing cutting-edge Cache subsystem design for Intel's AI SoCs. You …
… mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia groups including digital/DSP …
… component platforms with high speed Silicon photonics, transmit and receive amplifiers, controller ASIC’s with Marvell DSP’s. These components are made operational with a highly functional embedded firmware. The …
… Engineering, Computer Engineering, VLSI, or a related discipline. 14+ years of industry experience in ASIC or CPU Physical Design. Proven experience delivering successful products through complete physical …
… just "How" and "When." You understand that your job is to solve problems, not just manage a ticket queue. B asic Qualifications Bachelor’s Degree At least 7 years of experience in digital product management, with a track …
… a sufficient number of applications are received . Meet the Team Cisco Silicon One is the center of Cisco’s ASIC design and is driving the development of next-generation network devices for the 5G and AI era. Our …
… and architectural decisions, and review designs and implementations against them. Partner with hardware and ASIC architects to specify the security primitives firmware depends on, and define how they are used across the …
… and distributed engineering organizations. Deep expertise in ATE development for high-volume silicon, SoC, ASIC, or GPU-class products. Shown success leading organizations through NPI, silicon bring-up, …
… including a minimum of 3 years of technical program management experience Solid understanding of the ASIC/SoC design, verification, and bring-up/productization flow, and a clear understanding of where DFX fits: …
Pay posted by employer$220,920–$311,890 USD per year
… SoCs, or custom ASICs. • 5+ years of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). • 3+ years leading silicon design and/or …
… C, C++, and Python, with experience in embedded development environments. Experience with FPGA, SoC design, ASIC development, or other semiconductor platforms, with an understanding of hardware/software interactions. …
… component platforms with high-speed Silicon photonics, transmit and receive amplifiers, controller ASIC’s with Marvell DSP’s. These components are made operational with a highly functional embedded firmware. The …
… for next-generation optical engines (400G/lane CPO and beyond) Perform co-design across photonics, analog/ASIC design, and packaging teams to optimize performance, power efficiency, and signal integrity Perform …
… between them. Co-design noise features with Speed, Power, Reliability, Circuit Design, Power-Architecture, ASIC, and platform teams. You're the connective tissue across the codesign web. Work with other team members to …
Pay posted by employer$256,050–$361,480 USD per year
… or PhD in Electrical Engineering, Computer Science, or a related field. - 12+ years of experience in ASIC/SoC design and verification with a Bachelor's degree, 8+ years with a Master's degree, or 6+ years with a …