ASIC Engineer · AnywhereEdit
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651 matching jobs for “ASIC Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Cisco Systems

Hardware Engineer I (Full-Time) - United States

San Jose, California, United States +2 locations

Pay posted by employer$95,800–$139,700

… all the way through to high volume manufacturing. Creative Hardware Engineering positions available in: ASIC Design and Verification System/Board Design Circuit Board Layout Hardware Automation, Validation and Test …

Added Oct 30, 2026

HP

HP PageWide Web Press R&D Software Engineer

Corvallis, Oregon, United States

  • Full time
  • Reg Employee

Pay posted by employer$93,400–$135,400 USD per year

… configuration, and state management. Firmware / Embedded: Real-time device control, interactions with ASIC and FPGA, and diagnostics Innovation & AI-Assisted Capabilities (Optional) Apply AI-assisted techniques to …

Added Oct 12, 2026

Hewlett Packard Enterprise

Sr Network Test Engineer — Data Center Fabrics

Bengaluru, Karnataka, India

… PoC reviews and technical deep-dives. Test and verify SAI (Switch Abstraction Interface) integration and ASIC driver behavior Validate optical modules across various speeds, breakout configurations, and transceiver …

Added Nov 3, 2026

Cisco Systems

High-Speed SerDes Design Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$171,600–$245,000

… mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia groups including digital/DSP …

Added Oct 27, 2026

Marvell Technology

Physical Design Engineer Intern, MS - Summer 2027

Santa Clara, California, United States +6 locations

  • Internship

… teams focus their design work on supporting architecture to GDSII (Graphic Data System) implementation of ASIC and processor designs. Other teams focus on timing analysis for future designs of our next-gen …

Added Nov 3, 2026

Marvell Technology

Physical Design Engineer Intern, BS - Summer 2027

Santa Clara, California, United States +6 locations

  • Internship

… teams focus their design work on supporting architecture to GDSII (Graphic Data System) implementation of ASIC and processor designs. Other teams focus on timing analysis for future designs of our next-gen …

Added Nov 3, 2026

Cisco Systems

Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia groups including RF design, …

Added Oct 27, 2026

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.

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