583 matching jobs for “ASIC Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Cisco Systems

ASIC DFT DV Technical Lead

Bengaluru, Karnataka, India

Added Oct 27, 2026

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Nvidia

ASIC Physical Design and Timing Engineer - New College Grad 2026

Santa Clara, California, United States

… join the team and see how you can make a lasting impact on the world. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of …

Added Oct 31, 2026

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Nvidia

ASIC Engineer, Networking Chip Design - New College Grad 2027

China, Shanghai

We are now looking for Chip Design Engineer for the Switch Silicon group. As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a …

Added Oct 27, 2026

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Boeing

Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)

USA - El Segundo, CA +1 location

In person
Full time
Regular

Pay posted by employer$98,600–$133,400

… systems, advancing U.S. leadership in space while amplifying human creativity and intelligence. As a Boeing engineer, you’ll join a diverse, collaborative team solving high‑impact challenges in complex semiconductor design. …

Added Oct 12, 2026

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RTX

ASIC/FPGA Quality Engineer (Onsite - Melbourne, FL or Cedar Rapids, IA)

Melbourne, Florida, United States +1 location

… to join our Avionics Design Quality Assurance (DQA) team. We are looking for an experienced Electrical Engineer who is interested in applying their technical skills and experiences and working together with others to …

Added Oct 27, 2026

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Cisco Systems

ASIC Design Verification Engineer || Verilog, UVM, Testbench | Emulation || Exp 7+ years

Bengaluru, Karnataka, India

Added Oct 27, 2026

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Cisco Systems

ASIC Design Verification Engineer || Verilog, UVM, Testbench | Simulation || Exp 7+ years

Bengaluru, Karnataka, India

Added Oct 27, 2026

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Cisco Systems

ASIC Engineering Technical Leader- IC Package Design

Bengaluru, Karnataka, India +1 location

… Experience with industry-standard EDA tools for layout and design Preferred Qualifications Experience in ASIC package design, including pinout optimization and high-speed routing Knowledge of silicon floor planning, …

Added Oct 27, 2026

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Cisco Systems

Senior Asic Design - Cisco Silicon One

Caesarea, Israel

Added Oct 27, 2026

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Boeing

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$98,600–$133,400

ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead) Company: …

Added Oct 12, 2026

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Cisco Systems

ASIC High Speed AMS Technical Leader

Carlsbad, California, United States +1 location

Pay posted by employer$192,400–$275,800

… Your Impact Build the optical backbone of the AI revolution. As our High-Speed Analog/Mixed-Signal Design Engineer, you will directly lead the electrical specifications, custom circuit design, and verification strategies …

Added Oct 27, 2026

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Cisco Systems

ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Experience - 4 to 8 years

Bengaluru, Karnataka, India +1 location

… requires the candidate to have the ability to craft solutions and debug with minimal mentorship. You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of …

Added Oct 27, 2026

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Cisco Systems

ASIC Design Verification Engineer | Simulation & Emulation , Test methodologies | 7 to 11 Years | Bangalore

Bengaluru, Karnataka, India

Added Oct 27, 2026

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Cisco Systems

Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)

San Jose, California, United States +5 locations

Pay posted by employer$186,900–$267,700

… and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our …

Added Oct 27, 2026

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Cisco Systems

Hardware ASIC Packaging SI/PI Simulation and Design Lead (Hybrid)

San Jose, California, United States +10 locations

Pay posted by employer$186,900–$267,700

Added Oct 27, 2026

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Boeing

ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$119,850–$162,150

… How to make your application stand out : Please include a cover letter or brief summary of relevant DFT or ASIC physical design experience and specific examples of impact (e.g., achieved timing closure on X‑nm blocks, …

Added Oct 12, 2026

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Cisco Systems

ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Exp 4 to 8 years

Bengaluru, Karnataka, India +2 locations

Added Oct 28, 2026

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Cisco Systems

ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years

Bengaluru, Karnataka, India +1 location

Added Oct 27, 2026

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Cisco Systems

ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Bengaluru, Karnataka, India

… and efficient performance. • Support testing of design in emulation. • Lead all aspects of and manage the ASIC bring-up process. Minimum Qualifications • Bachelor’s degree or master’s Degree in equivalent experience in …

Added Oct 27, 2026

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Cisco Systems

Principal Hardware Systems Architect - ASIC (Silicon One) Ecosystem Integration & Product Strategy (Hybrid)

San Jose, California, United States

Pay posted by employer$233,900–$330,400

Added Oct 27, 2026

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Cisco Systems

ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Exp 4 to 8 years

Bengaluru, Karnataka, India +2 more

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Minimum Qualifications · employer excerpt

* Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 4-8 years of experience.
* Knowledge of the latest innovative trends in DFT, test and silicon engineering.
* Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
* Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
* Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

3 more in the full description below.

About this opportunity

Original employer description

Meet the Team:

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Your Impact:

* Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.

* Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.

* Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.

* Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

* The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Qualifications:

* Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 4-8 years of experience.

* Knowledge of the latest innovative trends in DFT, test and silicon engineering.

* Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.

* Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime

* Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

* Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.

* Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime

* Experience working with Gate level simulation, debugging with VCS and other simulators.

Preferred Qualifications:

* Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687

* Strong verbal skills and ability to thrive in a multifaceted environment

* Scripting skills: Tcl, Python/Perl.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Disclaimer

To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:

be in direct response to an application you have submitted through the company career site
begin with screening or an interview
originate from a Cisco email address, and
be conducted across email, phone, or WebEx

Cisco will never make a job offer without conducting an interview process or ask you for money in any way. If you have been requested to apply for a role or have received an offer from a site other than https://careers.cisco.com or cisco.wd5.myworkday.com, do not provide any personal identifying information, including your Aadhaar or other personal identifying number, birth certificate, banking information, driver's license, or passport.

If you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.

Why this result? · Employer labels

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