336 matching jobs for “ASIC Verification Engineer”

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Intel

Senior Design Verification Engineer - Neuromorphic Computing

Hillsboro, Oregon, United States +4 locations

Pay posted by employer$122,440–$232,190 USD per year

… the versatility demanded by modern AI workloads. Position Overview We are seeking experienced pre-silicon verification engineers who are passionate about driving innovation at the intersection of advanced semiconductor …

Added Oct 27, 2026

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Cisco Systems

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Pune, Maharashtra, India

… technologies including AI/ML workloads, and next-generation data center architectures. Your Impact As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept …

Added Oct 27, 2026

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Nvidia

GPU Verification Engineer - New College Grad 2026

Westford, Massachusetts, United States

We are now looking for a GPU Verification Engineer - New College Grad 2026! NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the …

Added Oct 29, 2026

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Nvidia

ASIC Design Engineer - New College Grad 2027

Santa Clara, California, United States

… people in the world and there has never been a more exciting time to join our team! We are seeking an ASIC Design Engineer - New College Graduate to implement the world’s leading SoC's and GPU's. This position …

Added Oct 27, 2026

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Boeing

ASIC / FPGA Digital Design Engineer – (Lead or Senior)

USA - El Segundo, CA +1 location

Full time
Regular

Pay posted by employer$146,200–$197,800

ASIC / FPGA Digital Design Engineer – (Lead or Senior) Company: Boeing Space, Intelligence & Weapons Systems has …

Added Oct 12, 2026

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Boeing

ASIC / FPGA Digital Design Engineer – (Associate or Experienced)

USA - El Segundo, CA +1 location

Full time
Regular

Pay posted by employer$98,600–$133,400

ASIC / FPGA Digital Design Engineer – (Associate or Experienced) Company: Boeing Space, Intelligence & Weapons …

Added Oct 12, 2026

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RTX

Sr Principal Electrical Engineer - ASIC/FPGA (Onsite)

US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A

… and defense. We are seeking an experienced and highly motivated Senior Principal Electrical or Computer Engineer to support the design, development, and integration of advanced digital ASIC and FPGA solutions for …

Added Oct 27, 2026

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RTX

Senior Principal Electrical Engineer (FPGA/ASIC) - HYBRID

Cedar Rapids, Iowa, United States

… Join us and help shape the future of aerospace and defense. We are hiring a Senior Principal Electrical Engineer (P5) for our growing Avionics FPGA/ASIC team in Cedar Rapids, IA. This position is for a highly experienced …

Added Oct 27, 2026

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Nvidia

Senior Design Verification Engineer - GPU Memory Subsystem

Durham, North Carolina, United States

… see how you can make a lasting impact on the world. We're looking for a talented, motivated Senior Design Verification Engineer to join our GPU memory subsystem team in Durham, NC. Looking to join a dynamic team solving …

Added Oct 27, 2026

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Cisco Systems

Leader, ASIC Engineering

Hsinchu, Taiwan, Taiwan +1 location

• Test Architecture & Development: Drive test program development and verification on automated test equipment (Advantest V93000 / SmarTest 7 & SmarTest 8) across digital, high-speed SerDes, …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer, GPU Core Pipeline IP

Bengaluru, Karnataka, India

NVIDIA is seeking a highly enthusiastic and motivated Design Engineer to design and implement the next generation of control subsystems for the world’s leading GPUs. This …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC Engineer - Post Silicon Validation

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… Join us to power the future of the digital world. Your Impact: In this role as a Post-Silicon Validation Engineer, you will be responsible for: Planning and setting up Silicon Bring-up infrastructure, including system …

Added Oct 31, 2026

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Nvidia

ASIC Physical Design Engineer - New College Grad 2027

China, Shanghai

… of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, …

Added Oct 27, 2026

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Cisco Systems

Design Verification Technical Leader

Carlsbad, California, United States +1 location

Pay posted by employer$192,400–$275,800

… Cisco’s industry-defining Silicon One Optics group, you won’t just follow the future of networking—you’ll engineer it. We are actively building the hyper-scalable optical transceivers and modules (800G, 1.6T, and beyond) …

Added Oct 27, 2026

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Intel

Senior Formal Verification Engineer – AI SoC Development

Folsom, California, United States +3 locations

Pay posted by employer$220,920–$311,890 USD per year

… driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs …

Added Oct 27, 2026

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RTX

FPGA Verification Engineer II (Onsite)- Active Secret

US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A

Verification environment architecture and design using SystemVerilog with OVM/UVM Creation of written test plan, …

Added Oct 27, 2026

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Cisco Systems

Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

Bengaluru, Karnataka, India

… networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design verification background with hands-on experience in System …

Added Oct 27, 2026

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Cisco Systems

ASIC STA Technical Lead

San Jose, California, United States

Pay posted by employer$186,900–$267,700

… the future of the digital world. Your Impact You will be in the Silicon One development organization as an ASIC DFT STA Technical Lead. You are a detail-oriented STA engineer with strong analytical skills and a deep …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC DFT DV Engineer (Hybrid)

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification. Minimum Qualifications Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC DFT DV Engineer (Hybrid)

San Jose, California, United States +1 location

Pay posted by employer$167,700–$245,200

… ATE screening, in-system test, debug and diagnostics needs of the design Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation …

Added Oct 27, 2026

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Cisco Systems

Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

Bengaluru, Karnataka, India

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Minimum Qualifications · employer excerpt

BS/MS and 15+/13+ years respectively of hands-on experience in large-scale, high-performance ASIC.
Have led a design team for a minimum of 5+ years

About this opportunity

Original employer description

Meet the Team
Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Your Impact
Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Leader. You will have an ASIC design verification background with hands-on experience in System Verilog and UVM methodology with in-depth knowledge of C++, scripting as well as ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.

Leads ASIC engineering teams to deliver high-performance, high quality and reliable ASICs for Cisco's diverse product platforms.
Leads teams in defining and verifying ASICs and ASIC subsystems to ensure alignment with stringent quality requirements for deployment across Cisco’s platforms.
Drives collaboration cross-functionally to achieve high-volume production with uncompromised quality.
Collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.
Defining and Building UVM/System Verilog testbenches from scratch or enhancing existing testbenches with focus on reuse
Defining new DV methodologies or enhancing the existing methodologies
In-depth understanding of the architecture, and identification of problems and solutions.
End-to-end verification of one or more design blocks simultaneously while helping full chip team with integration and support.
Test plan generation, review, planning and execution, meeting all criteria of ASIC group.
Help in developing Emulation infrastructure using C/C++, that has to work with UVM based verification environment.
Gate level simulation and SDF back annotation for blocks as part of pre-silicon verification.
Code and Functional coverage-based simulation run, coverage collection, merging and working with designers to fill coverage holes.
Participating in all phases during ASIC development – RTL Verification, Emulation and post-silicon validation
Recommending best practice, identifying and suggesting innovative solutions to improve efficiency and quality
Leading and mentoring team of junior engineers in addition to the assigned task.
Strong focus on efficiency, quality, reusability.
Drives design verification solutions across the business. Ensure culture of code reviews and postmortems.
Act as the design verification leader, owning and leading all the above aspects, including driving the technical decisions made at the program level with rest of the dv teams, conducting weekly dv meetings, sync-ups with stake holders and cross functional teams like Architecture, Design, Emulation, SW, PSV.

Minimum Qualifications

BS/MS and 15+/13+ years respectively of hands-on experience in large-scale, high-performance ASIC.
Have led a design team for a minimum of 5+ years

Must have prior experience of developing UVM based infrastructure from scratch in more than one projects.
Ability to handle complex features/parts of chip independently.
Quick learner must be able to work in a fast pace dynamic environment and must be able to deliver quality even in aggressive schedule.
Strong teamwork quality – must be able to work in a highly collaborative team.
Overseeing reusability, comes up reusable solution to improve efficiency. Must always focus on efficiency and quality.
Ability to build, lead and mentor a team of engineers and ensuring quality delivery as a team.
Proficient in merging and analyzing code coverage data generated functional simulation
Good working knowledge in C, C++ programming and debugging skills
Experienced in system debug and SW/HW bring-up, system validation of silicon towards FCS.
Hardware Emulation Platforms and tools (such as EVE, Veloce)
Good written/verbal interpersonal skills and leadership skills.

Preferred Qualifications

Worked in DV methodology and definition of high-scale, high-performance ASICs.
Planning overall DV architecture strategy and defining the requirements.
Conducting & leading various test plan reviews.
Driving complex debugs and system level integration aspects
Valid experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
Mentoring the senior resources in the team on DV and DV methodologies.
Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
Excellent communication skills both verbal and written

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Disclaimer

To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:

be in direct response to an application you have submitted through the company career site
begin with screening or an interview
originate from a Cisco email address, and
be conducted across email, phone, or WebEx

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