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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.
Santa Clara, California, United States
… human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a growing and …
Irvine, California, United States
… Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal, Digital IC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the high performance …
Santa Clara, California, United States +1 location
Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed …
USA-Mendota Heights-Northland +2 locations
Pay posted by employer$109,700–$175,500 USD per year
The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for …
Bengaluru, Karnataka, India
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
Bengaluru, Karnataka, India
The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, …
Santa Clara, California, United States
We are now looking for a Senior Post-Silicon Validation Engineer to join our team! NVIDIA has continuously reinvented itself over the past two decades. Our invention of the …
Hillsboro, Oregon, United States +4 locations
Pay posted by employer$122,440–$232,190 USD per year
… demanded by modern AI workloads. Position Overview We are seeking an experienced design automation engineer passionate about driving innovation at the intersection between emerging semiconductor technology, physical …
Santa Clara, California, United States
We are looking for a talented Senior System Software Engineer to help build NVIDIA Halos, our full-stack safety platform for physical AI: autonomous vehicles, humanoids, …
Folsom, California, United States +2 locations
Pay posted by employer$164,470–$232,190 USD per year
… digital lives. Come join us and do something wonderful. The Role and Impact: As a GPU Physical Design Engineer, you will play a critical role in the physical implementation of cutting-edge GPU designs from RTL to GDS, …
Bengaluru, Karnataka, India
… and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, IO planning and …
Nuremberg, Bavaria, Germany
… Design, implement, and maintain high-reliability embedded firmware in C (and C++) for microcontroller- and ASIC-based controllers operating in optical modules at 100G/s and above. Implement Device Diagnostics & Control: …
United States-Illinois-Rolling Meadows
Pay posted by employer$119,600–$179,400
… decisive advantage to the warfighter. Come be a part of our mission! We are seeking a talented FPGA Design engineer with signal processing experience to join our growing team in Rolling Meadows, IL. As an FPGA Design …
Santa Clara, California, United States +1 location
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and …
Austin, Texas, United States +2 locations
Pay posted by employer$143,800–$230,000 USD per year
… Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms …
Austin, Texas, United States +2 locations
Pay posted by employer$121,900–$195,000 USD per year
… Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms …
Milpitas, California, United States
Pay posted by employer$154,900–$225,300
… shaping Cisco's ground-breaking solutions by design ing, developing, and test ing some of the most complex ASIC s being developed in the industry. The Cisco Service Provider Routing Hardware Engineer ing team develops …
Yokneam +1 location
… with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools. Integrate new AI based design flows Work with various teams to drive …
Broomfield, Colorado, United States +3 locations
Pay posted by employer$121,900–$195,000 USD per year
The candidate will be responsible for leading and executing Synthesis, Static Timing Analysis (STA), Formal Verification, and low-power implementation activities of Mixed Signal (MXS) blocks. Additionally, this role acts as the …
Location reference: GeoNames (CC BY 4.0), normalized by Referizz.
