279 matching jobs for “Senior ASIC Design Engineer”

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Analog Devices

Senior Engineer, DFT Engineering

Bengaluru, Karnataka, India

Collaborate with the design team to ensure efficient and effective testability of complex integrated circuits. Design and implement DFT …

Added Nov 3, 2026

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Nvidia

Senior System Verification Engineer

Austin, Texas, United States

… as well as its largest total available market opportunity. We are now looking for a highly motivated engineer to join this dynamic and innovative platform verification team. In this role, you will apply your RTL …

Added Oct 27, 2026

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Nvidia

Senior Product Development Engineer

Santa Clara, California, United States

… Doing As an integral part of product engineering, you will drive our latest architecture designs to market. Design FT (final test) test processes to enhance manufacturing efficiency for our latest GPUs, built in …

Added Oct 31, 2026

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Nvidia

Senior Memory Controller Verification Engineer

Santa Clara, California, United States +4 locations

NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our GPU Memory Subsystem IP verification Team! At NVIDIA, we have crafted a team …

Added Oct 31, 2026

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RTX

Senior Electrical Engineer - FPGA (Onsite)

Marlborough, Massachusetts, United States

Requirements capture, FPGA digital architecture and design using RTL, timing closure, verification, and system integration Optimize FPGA implementations to meet …

Added Oct 27, 2026

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Cisco Systems

Senior Hardware Engineer (Datacenter Switch)

Hsinchu, Taiwan, Taiwan +1 location

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 29, 2026

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Nvidia

Senior QA Software Engineer, Networking

Warsaw, Mazovia, Poland +1 location

What if your Python automation caught a critical ASIC bug before the physical silicon was even manufactured? At NVIDIA, our simulation platforms make that happen …

Added Oct 27, 2026

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Marvell Technology

Senior Principal Engineer-DFT

Santa Clara, California, United States

Full time
Regular

… organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina — and we are looking for a senior experienced technical leader to serve as a DFT Lead on our next-generation ODSP programs. What You Can …

Added Nov 5, 2026

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RTX

Senior Electrical Engineer - FPGA (Onsite)

Melbourne, Florida, United States

… of the global market. Join us and help shape the future of aerospace and defense. We are looking for a Senior Electrical Engineer - FPGA to join our team in Melbourne, FL. This position will work closely with our …

Added Oct 27, 2026

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Nvidia

Senior FPGA Prototyping Engineer - Hardware

Santa Clara, California, United States

… of our next generation GPUs and SOCs on standard FPGA prototyping platforms. We are now looking for a Senior FPGA Prototyping Engineer to join our Emulation team onsite in Santa Clara, CA. What you'll be doing: Build …

Added Oct 27, 2026

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Nvidia

Senior Cell Modeling and Verification Engineer

Santa Clara, California, United States

… world and there has never been a more exciting time to join our team! The NVIDIA VLSI team is looking for a Senior Cell Modeling and Verification Engineer with strong experience in hardware design and methodologies to help …

Added Oct 27, 2026

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GE HealthCare Technologies

Senior FPGA & Digital Hardware Engineer

Waukesha, Wisconsin, United States

… the digital electronics behind next-generation Magnetic Resonance imaging systems. As a Digital Hardware Engineer on our Digital Controls & Mixed Signal Engineering team, you will contribute to circuit boards and …

Added Oct 27, 2026

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Cisco Systems

System Hardware Board Design Engineering Lead (Onsite)

Milpitas, California, United States

Pay posted by employer$171,600–$245,000

… and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our …

Added Oct 27, 2026

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Cisco Systems

Senior Analog Layout Engineer

Carlsbad, California, United States +1 location

Pay posted by employer$149,100–$218,100

Added Oct 27, 2026

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Nvidia

Senior Power Analysis and Optimization Engineer

Santa Clara, California, United States +1 location

We’re looking for a Senior Power Architecture & Optimization Engineer to push the limits of energy efficiency using advanced analytics …

Added Oct 27, 2026

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Nvidia

Senior Systems Prototyping and Emulation Engineer

Santa Clara, California, United States

Are you passionate about DGX systems connecting multiple ASIC chips together, FPGA prototyping, and hardware emulation? Are you interested in pushing the boundaries of …

Added Oct 27, 2026

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Nvidia

Senior Post-Silicon Characterization Engineer

Israel, Yokneam

NVIDIA Networking IC Product Engineering team is looking for a Post Si Characterization and Validation engineer, to take part of Network ASIC, SOC and SiPh ICs characterization efforts of speed, logic, memory, power and …

Added Oct 27, 2026

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Intel

Sr Deep Learning Verification Engineer

Leixlip, Leinster, Ireland

Full time
Regular

The Role and Impact As a Sr Deep Learning Hardware Verification Engineer, you will play a pivotal role in shaping the future of AI hardware by validating and optimizing …

Added Oct 27, 2026

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Nvidia

Principal Chip Lead, Silicon Co-Design Group

Santa Clara, California, United States

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our …

Added Oct 27, 2026

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Nvidia

Senior System Software Engineer - Halos

Santa Clara, California, United States

We are looking for a talented Senior System Software Engineer to help build NVIDIA Halos, our full-stack safety platform for physical AI: …

Added Oct 31, 2026

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Analog Devices

Senior Engineer, DFT Engineering

Bengaluru, Karnataka, India

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Qualifications · employer excerpt

Bachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.
3-8 years of hands-on experience in DFT methodologies and techniques.
Strong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.
Hand-on experience/expertise in Siemen’s DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.
Proficiency in scripting languages such as Perl, Tcl, and/or Python for automation.

3 more in the full description below.

About this opportunity

Original employer description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

Job Description:

We are seeking a skilled and experienced DFT Engineer to join our VLSI design team. The ideal candidate should have a strong background in Design for Testability (DFT) techniques, including LBIST (Logic Built-In Self-Test), ATPG (Automatic Test Pattern Generation), DFT DRC (Design Rule Checking), MBIST (Memory Built-in Sefl-Test), Boundary Scan, JTAG and Analog/Phy DFT.

Responsibilities:

Collaborate with the design team to ensure efficient and effective testability of complex integrated circuits.
Design and implement DFT features such as scan chains, compression, and built-in self-test structures to enhance testability.
Conduct DFT DRC checks in RTL/Netlist database to ensure compliance with DFT guidelines and rules.
Utilize Siemen’s DFT tool to perform DFT analysis and optimize testability metrics.
Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models using on-chip test compression techniques.
MBIST Design (including repair) and Verification using Siemen’s EDA tool.
Validation of DFT structures/patterns in RTL, Netlist with and without SDF.
Work closely with the verification team to define and implement DFT verification plans.
Work closely with physical design team for DFT implementation/constraints strategy for synthesis/STA.
Analyze and debug test failures and collaborate with the test engineering team to resolve issues.
Provide guidance and mentorship to junior DFT engineers.

Qualifications:

Bachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.
3-8 years of hands-on experience in DFT methodologies and techniques.
Strong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.
Hand-on experience/expertise in Siemen’s DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.
Proficiency in scripting languages such as Perl, Tcl, and/or Python for automation.
Solid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks and ASIC design flow.
Excellent problem-solving skills and ability to work effectively in a team-oriented environment.
Strong communication and interpersonal skills.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

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