279 matching jobs for “Senior ASIC Design Engineer”

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Cisco Systems

ASIC DFT Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$155,000–$222,600

include: Support DFT implementation for ASIC / SoC blocks and subsystems Implement and validate scan insertion, scan compression, OCC, MBIST, boundary …

Added Oct 28, 2026

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Nvidia

Senior Mask Design Engineer - Hardware

Santa Clara, California, United States +1 location

… to the world. This is our life’s work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, …

Added Oct 31, 2026

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Marvell Technology

Senior Staff Digital Design Engineer

Irvine, California, United States

Full time
Regular

… and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Digital ASIC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the …

Added Nov 3, 2026

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Nvidia

Senior Mask Layout Design Engineer

Santa Clara, California, United States +1 location

… delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include …

Added Oct 31, 2026

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Nvidia

Senior Mask Design Engineer - Hardware

Santa Clara, California, United States 2 postings

… work, to amplify human creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse …

Added Oct 31, 2026

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Nvidia

Senior Mask Design Engineer - Hardware

Santa Clara, California, United States

… human creativity and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! Someone who is excited to join a …

Added Oct 31, 2026

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Nvidia

Senior Mask Design Engineer - Hardware

Santa Clara, California, United States

Added Oct 31, 2026

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Nvidia

Senior Mask Layout Design Engineer

Santa Clara, California, United States +1 location

Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals …

Added Oct 27, 2026

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Nvidia

Senior Chip Design Verification Engineer

Israel, Yokneam +1 location

NVIDIA's Chip Design group is looking for best-in-class Verification Engineers to join our outstanding Silicon Engineering team, …

Added Oct 27, 2026

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Nvidia

Senior Chip Design Verification Engineer

Israel, Tel Aviv

NVIDIA is looking for a best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon Engineering team, developing the …

Added Oct 27, 2026

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Intel

GPU Senior Logic Design Engineer

Bengaluru, Karnataka, India

Full time
Regular

GPU Senior Logic Design Engineer: Develop logic design, generate/write Register Transfer Level (RTL) code, and perform …

Added Oct 27, 2026

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RTX

Senior FPGA Design Engineer (Hybrid)

US-PR-AGUADILLA-110 ~ Rd 110 N Km 28.8 ~ RD110

Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration …

Added Oct 27, 2026

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Marvell Technology

Sr. Staff Engineer, Physical Design

Da Nang, Da Nang City, Vietnam

Full time
Regular

… trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Central Engineering ASIC Design Services Team within Marvell provides chip solutions for next generation 5G carriers, cloud data …

Added Nov 3, 2026

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Intel

Senior Core Design Verification Engineer

Malaysia, Penang

Full time
Regular

The Role and Impact As a CPU Design Verification Engineer, you will play a pivotal role in ensuring the functionality and reliability of …

Added Oct 27, 2026

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Broadcom

IC Design Engineer

Fort Collins, Colorado, United States

Pay posted by employer$91,100–$146,000 USD per year

ASIC Design Engineer Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in …

Added Nov 12, 2026

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Palo Alto Networks

Sr FPGA Design Engineer (NetSec)

Office - USA - CA - Headquarters

… modules, and hardware acceleration platforms for our next-generation firewalls. You will own FPGA design from architecture and specification through RTL, timing closure, synthesis, and lab bring-up, collaborating …

Added Oct 27, 2026

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Intel

Senior GPU Physical Design Engineer

Folsom, California, United States +2 locations

Full time
Regular

Pay posted by employer$164,470–$232,190 USD per year

… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …

Added Oct 27, 2026

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Marvell Technology

Senior Staff Engineer, Physical Design

Austin, Texas, United States

Full time
Regular

include: Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in …

Added Nov 3, 2026

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Nvidia

Senior SOC Design Engineer - Networking Group

Bengaluru, Karnataka, India

We are currently seeking an expert SOC Design and Integration Engineers with strong design fundamentals to work in Networking chip design group. You'll …

Added Oct 27, 2026

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Northrop Grumman

Principal/ Sr. Principal FPGA Design Engineer

United States-Illinois-Rolling Meadows

Pay posted by employer$119,600–$179,400

… Space Systems today! Our team is chartered with providing the skills, innovative technologies to develop, design, produce and sustain optimized product lines across the sector while providing a decisive advantage to the …

Added Nov 3, 2026

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Cisco Systems

ASIC DFT Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$155,000–$222,600

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Minimum Qualifications · employer excerpt

Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
Experience with ASIC DFT implementation or validation
Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
Experience with stuck-at and transition fault models

2 more in the full description below.

About this opportunity

Original employer description

This is a hybrid role than can be performed three days per week from our San Jose, CA office.

Meet the Team

Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.

Your Impact

We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product engineering, and test teams to help deliver high-quality test coverage and manufacturability for advanced semiconductor designs. Key responsibilities include:

Support DFT implementation for ASIC / SoC blocks and subsystems
Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic
Run DFT rule checks and debug scan, clock, reset, and test-mode issues
Generate and validate ATPG patterns for stuck-at, transition, and other required fault models
Analyze test coverage, pattern count, compression results, and ATPG reports
Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues
Work with RTL and verification teams to ensure DFT requirements are correctly implemented
Support block-level and full-chip DFT integration activities
Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable
Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting
Support silicon debug, diagnosis analysis, and yield-learning activities as needed
Document DFT implementation results, known issues, waivers, and signoff status

Minimum Qualifications:

Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
Experience with ASIC DFT implementation or validation
Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
Experience with stuck-at and transition fault models
Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures
Scripting experience using Tcl, Python, Perl, or shell

Preferred Qualifications

Experience with hierarchical DFT methodology and block-level signoff
Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows
Experience with MBIST insertion, memory test validation, or BISR flows
Familiarity with gate-level simulation, SDF timing, and pattern validation
Exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug
Experience working on advanced-node ASICs, networking ASICs, or high-performance SoCs
Ability to improve automation, regression checks, and DFT reporting dashboards
Experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation
Scripting experience using Tcl, Python, Perl, or shell
Experience troubleshooting problems related to ASIC DFT and working with cross-functional teams.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$155,000.00 - $256,000.00

Non-Metro New York state & Washington state:

$138,100.00 - $227,900.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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