279 matching jobs for “Senior ASIC Design Engineer”

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Cisco Systems

Senior ASIC Layout Engineer

Armenia

We are hiring an ASIC Engineer to own standard cell layout for our next-generation ASICs on innovative FinFET and GAA nodes. You …

Added Oct 28, 2026

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Nvidia

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Santa Clara, California, United States +1 location

As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level …

Added Oct 27, 2026

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Hewlett Packard Enterprise

Senior ASIC Verification Engineer

Sunnyvale, California, United States

Pay posted by employer$158,500–$321,000 USD per year

… your own limits for learning, achievements, and rewards. Position Summary We are seeking a highly motivated Senior ASIC Verification Engineer to join our networking silicon development team. Key Responsibilities: Own and …

Added Nov 3, 2026

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Nvidia

Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

Santa Clara, California, United States +4 locations

… best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is seeking a Senior ASIC Compose Verification Infrastructure and Tools Engineer to advance the systems that qualify, integrate, …

Added Oct 27, 2026

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Hewlett Packard Enterprise

Senior ASIC Verification Engineer

Sunnyvale, California, United States

Pay posted by employer$158,500–$321,000 USD per year

… develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical …

Added Nov 3, 2026

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Nvidia

Senior ASIC Verification Engineer

Austin, Texas, United States

… human inventiveness and intelligence. The NVIDIA System-On-Chip (SOC) group is looking for an experienced ASIC Verification Engineer! In this position you will have the chance to create a high-level and broad impact at …

Added Oct 27, 2026

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Cisco Systems

Senior Asic Design - Cisco Silicon One

Caesarea, Israel

Meet the Team Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development. Our engineers cover the full spectrum of chip design: …

Added Oct 27, 2026

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Hewlett Packard Enterprise

Senior ASIC verification engineer

Roseville, California, United States

Pay posted by employer$158,500–$321,000 USD per year

Added Nov 3, 2026

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Boeing

ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal)

USA - Albuquerque, NM

In person
Full time
Regular

Pay posted by employer$136,850–$185,150

ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal) Company: The Boeing Company Boeing …

Added Oct 15, 2026

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Nvidia

Senior ASIC Verification Engineer - GPU

Santa Clara, California, United States

At NVIDIA, we push the boundaries of computing innovation. Our ASIC Verification Engineers focus on developing the world’s top SoCs and GPUs. Joining us as a Senior ASIC …

Added Oct 27, 2026

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Nvidia

Senior ASIC Timing Engineer

Santa Clara, California, United States +3 locations

… join the team and see how you can make a lasting impact on the world. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of …

Added Oct 27, 2026

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Intel

Senior ASIC Verification Engineer

Israel, Haifa

Full time
Regular

… flow — planning, stimulus and checker development, coverage analysis, debug and more — and we look to our senior verification engineers to help steer that evolution. If you are energized by defining things that have …

Added Oct 27, 2026

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Intel

Senior ASIC DFT Engineer

Israel, Haifa

Full time
Regular

… We are intentional, fast adopters of AI as a working tool, and actively use AI throughout our architecture, design, verification, and development workflows. If you are energized by defining things that have never existed …

Added Oct 27, 2026

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Boeing

ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$119,850–$162,150

… with architecture, RTL, verification, DFT, and external backend partners. Position Responsibilities: Design and implement DFT architectures and test access mechanisms: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan …

Added Oct 12, 2026

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Nvidia

Senior ASIC Verification Engineer - GPU

Santa Clara, California, United States

NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the world’s leading GPUs. In this role, you will be doing unit level …

Added Oct 28, 2026

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Nvidia

Senior ASIC Verification Engineer - HSIO

Westford, Massachusetts, United States +1 location

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of the next generation of High Speed …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC RTL Engineer

San Jose, California, United States +1 location

Pay posted by employer$167,700–$245,200

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

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Marvell Technology

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Santa Clara, California, United States

Regular

… member of Marvell Central Engineering, you will play a leading role on developing next-generation Agentic design verification workflow and its add-on tools. You will have the opportunity to use your extensive design and …

Added Nov 3, 2026

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Cisco Systems

ASIC Layout Engineer

Armenia

We are hiring an ASIC Engineer to design and verify standard cells for our next-generation ASICs on innovative FinFET and GAA …

Added Oct 31, 2026

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Nvidia

ASIC Verification Engineer - Hardware

China, Shanghai

We are now looking for a ASIC Verification Engineer. NVIDIA SOC System-ASIC team is hiring a senior verification engineer. In this role, …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC RTL Engineer

San Jose, California, United States +1 more

Pay posted by employer$167,700–$245,200

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Minimum Qualifications · employer excerpt

Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 8 years of experience
Prior experience in Verilog/System Verilog coding.
Prior experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
Prior experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.

About this opportunity

Original employer description

The application window is expected to close on: 12/24/2026

Meet the Team:

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world

Your Impact:

You will be a key member of the Silicon One development organization, collaborating closely with Front-end RTL and backend physical design teams to gain a deep understanding of chip architecture. Your primary focus will be to drive high-quality Design for Test (DFT) RTL, ensuring robust and reliable silicon solutions that meet Cisco’s standards for performance and innovation. This cross-functional teamwork is essential to delivering advanced networking silicon aligned with Cisco Silicon One’s scalable and flexible architecture.

Minimum Qualifications:

Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 8 years of experience
Prior experience in Verilog/System Verilog coding.
Prior experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
Prior experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.

Preferred Qualifications:

Prior experience with power optimization techniques , power intent (UPF), power estimation.
Prior experience with DFT/MBIST is a plus
Prior experience with post-silicon debug

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$167,700.00 - $282,000.00

Non-Metro New York state & Washington state:

$149,100.00 - $250,900.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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