ASIC Engineer · AnywhereEdit
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621 matching jobs for “ASIC Engineer”

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Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

Broadcom

ASIC Package Design Project Manager

Fort Collins, Colorado, United States

  • Full time
  • Regular

Pay posted by employer$129,400–$207,000 USD per year

… related to package design: Package-Design lifecycle How the substrate and package fit into the overall ASIC design and manufacturing flows Design Data, including how it is created and used: .mcm, package …

Added Oct 5, 2026

Cisco Systems

ASIC Physical Design Engineer II (Full Time) - United States

San Jose, California, United States

Pay posted by employer$125,700–$203,100

… more, and work quickly. Join us to power the future of the digital world. Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. …

Added Oct 27, 2026

Cisco Systems

ASIC DFT Engineering Technical Leader

San Jose, California, United States +2 locations

Pay posted by employer$186,900–$267,700

… the future of the digital world. Your Impact You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL …

Added Oct 27, 2026

Marvell Technology

Principal ASIC/SoC Validation Lead - Photonic Fabric

Santa Clara, California, United States

  • Full time
  • Regular

… trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Principal Validation Engineer (Lead) will own the lab validation strategy and execution for advanced ASIC/SoC products integrating CXL …

Added Nov 3, 2026

Cisco Systems

ASIC Engineering Technical Leader- IC Package Design

Bengaluru, Karnataka, India +1 location

… Experience with industry-standard EDA tools for layout and design Preferred Qualifications Experience in ASIC package design, including pinout optimization and high-speed routing Knowledge of silicon floor planning, …

Added Oct 27, 2026

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.

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