635 matching jobs for “ASIC Design Engineer”

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Cisco Systems

Design Verification Technical Leader

Carlsbad, California, United States +1 location

Pay posted by employer$192,400–$275,800

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and …

Added Oct 27, 2026

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Broadcom

Senior Digital / Mixed-Signal IC Design or Verification Engineer

USA-Mendota Heights-Northland

Full time
Regular

Pay posted by employer$109,700–$175,500 USD per year

Senior Digital / Mixed-Signal IC Design or Verification Engineer Location: Mendota Heights, MN or Broomfield, CO Job Description Summary Join …

Added Oct 5, 2026

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Cisco Systems

Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia …

Added Oct 27, 2026

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Marvell Technology

Senior Staff Manager, Physical Design

Hsinchu City

Full time
Regular

Marvell is seeking a Senior Manager of Physical Design to lead project-level physical design execution and support team growth at the site. This role is …

Added Nov 3, 2026

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RTX

Senior Principal Electrical Engineer-FPGA Design - Onsite Tucson, AZ

Tucson, Arizona, United States

… department develops electronics for our weapon system products. We are responsible for the architecture, design, and documentation of deliverable FPGA embedded processing. We engage at the outset of the weapon system …

Added Oct 27, 2026

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Cisco Systems

Physical Design Technical Leader

San Jose, California, United States +1 location

Pay posted by employer$186,900–$267,700

Added Oct 27, 2026

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Cisco Systems

ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years

Bengaluru, Karnataka, India +1 location

… the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and …

Added Oct 27, 2026

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Cisco Systems

ASIC DFT Engineer || MBIST, SCAN, ATPG, JTAG || Exp 4 to 8 years

Bengaluru, Karnataka, India +2 locations

Added Oct 28, 2026

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Cisco Systems

ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Bengaluru, Karnataka, India

… scratch. • Maintain and improve existing DV environments. • Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus. • …

Added Oct 27, 2026

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Cisco Systems

Senior Analog/mixed-signal IC Design Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$194,600–$285,700

… metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed ()25Gb/s), and high accuracy, analog designs for optical communications …

Added Oct 27, 2026

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Cisco Systems

HW Design Leader- Cisco Silicon One

Caesarea, Israel

… and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we're able to think differently, experiment more, and …

Added Nov 1, 2026

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Nvidia

PCIe Design Verification Intern - Summer 2027

Austin, Texas, United States

… Science, Computer Engineering, Electrical Engineering or related degree. Exposure to computer architecture, ASIC design, or verification methodology is required. Familiarity with Object Oriented programing and/or …

Added Oct 27, 2026

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Nvidia

PCIe Design Verification Intern - Spring 2027

Santa Clara, California, United States

Added Oct 27, 2026

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Intel

Senior Technical Lead - CPU Physical Design

Bengaluru, Karnataka, India

Full time
Regular

We are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from floorplanning through signoff. The …

Added Oct 27, 2026

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Cisco Systems

System Hardware Board Design Engineering Lead (Onsite)

Milpitas, California, United States

Pay posted by employer$171,600–$245,000

… and data centers with a fully unified routing and switching portfolio. We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our …

Added Oct 27, 2026

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Cisco Systems

ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore

Bengaluru, Karnataka, India +1 location

Added Oct 27, 2026

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Cisco Systems

Advanced Packaging Design Engineering Team Lead (Hybrid)

San Jose, California, United States

Pay posted by employer$186,900–$267,700

Added Oct 30, 2026

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Intel

Sr Director, XSE Design Verification Engineering

Santa Clara, California, United States

Full time
Regular

Pay posted by employer$256,050–$361,480 USD per year

The Role and Impact As a Design Verification Engineering Manager, you will lead a dynamic team of design verification engineers responsible …

Added Oct 31, 2026

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Cisco Systems

Principal Hardware Systems Architect - ASIC (Silicon One) Ecosystem Integration & Product Strategy (Hybrid)

San Jose, California, United States

Pay posted by employer$233,900–$330,400

Added Oct 27, 2026

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Cisco Systems

Advanced Packaging Design Engineering Team Leader (Hybrid)

San Jose, California, United States

Pay posted by employer$214,100–$309,800

Added Oct 27, 2026

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Cisco Systems

Physical Design Technical Leader

San Jose, California, United States +1 more

Pay posted by employer$186,900–$267,700

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Minimum Qualifications · employer excerpt

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience

About this opportunity

Original employer description

The application window is expected to close on: 11/30/2026

Meet the Team

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

Don't just watch the AI revolution happen—build the physical backbone powering it. As a Physical Design Engineer at Silicon One Optics, you will floorplan, tape out, and physically realize our next-gen 800G, 1.6T, and multi-terabit optical transceivers and driver ICs. You'll directly shape the silicon photonics that power hyper-scale AI/ML data centers worldwide. If you want your silicon in the most demanding networks on the planet, this is where you need to be.

Full-Flow Ownership & First-Pass Tapeout: Lead end-to-end RTL-to-GDSII physical design implementation across advanced nodes, driving hierarchical floorplanning, complex mixed-signal macro placement, and signoff (STA, IR/EM, PV) to ensure first-pass silicon success.
Methodology & Flow Innovation: Architect and scale digital implementation flows, leveraging custom TCL/Python automation and close EDA vendor partnerships to elevate QoR, optimize turnaround time, and improve team-wide productivity.

Cross-Functional Design Convergence: Lead physical execution across PnR, CTS, MMMC timing closure, and ECO iterations, collaborating closely with RTL, Analog, DFT, Packaging, and CAD teams to resolve complex cross-domain bottlenecks.

Minimum Qualifications

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience

Prior experience in ASIC/SoC physical design and implementation in advanced tech nodes

Prior hands-on experience with the full physical design flow at block and/or chip level

Prior hands-on expertise in EDA tool flows, back-end sign-off criteria, and workflow automation utilizing Python, TCL, and Shell scripts to maximize turnaround time and execution efficiency.

Preferred Qualifications

Prior experience in closing designs with high-speed, high-density, macro-dominant, and I/O cell–intensive blocks

Prior experience in STA methodology, SDC timing constraint creation, analysis, and timing ECO generation for final sign-off timing closure.

Prior experience in physical design fundamentals with proven ability to identify, debug, and fix complex Electromigration (EM), IR drop, RC parasitic extraction, and crosstalk/glitch violations.

Prior hands-on experience with functional equivalence checking and functional ECOs

Prior experience in power grid design and optimization

Good understanding of the Standard-Cell IP, memory compiler IP Selection Criteria

Prior experience in integrating mixed-signal designs

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$186,900.00 - $307,800.00

Non-Metro New York state & Washington state:

$166,300.00 - $274,100.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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