316 matching jobs for “ASIC Verification Engineer”

How results work

Exact titles rank first, then title variations and keywords in descriptions. These labels aren't qualification scores. Without keywords, recently added jobs appear first.

GE Aerospace

Staff Engineer - FPGA Design/Verification

Grand Rapids, Michigan, United States +2 locations

Full time
Regular

Summary GE Aerospace is seeking an experienced Staff Engineer – FPGA Design/Verification to lead the development of custom logic for advanced avionics hardware. This …

Added Oct 27, 2026

Save job

RTX

FPGA/ASIC Engineer II (Onsite)

US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A

You will support requirements capture and ASIC / FPGA digital architecture. You will implement ASIC / FPGA digital design using RTL. You will support …

Added Oct 27, 2026

Save job

Nvidia

Senior ASIC Design Engineer - DFT

Santa Clara, California, United States

We are now looking for a Senior ASIC Design Engineer to join our DFT team! NVIDIA has continuously reinvented itself over two decades. Our …

Added Oct 27, 2026

Save job

Cisco Systems

ASIC DFT Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$155,000–$222,600

include: Support DFT implementation for ASIC / SoC blocks and subsystems Implement and validate scan insertion, scan compression, OCC, MBIST, boundary …

Added Oct 28, 2026

Save job

Cisco Systems

ASIC Physical Design CAD Engineer

Caesarea, Israel +1 location

Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One …

Added Oct 27, 2026

Save job

RTX

Principal FPGA/ASIC Engineer (Onsite)

El Segundo, California, United States +1 location

Verification environment architecture and design using SystemVerilog with UVM/UVM-F Creation of written test plan, …

Added Oct 27, 2026

Save job

Nvidia

ASIC Design Engineer – Clocks IP

Santa Clara, California, United States +1 location

The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The …

Added Oct 27, 2026

Save job

Cisco Systems

ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Bengaluru, India

… cluster and higher-level environments with mix of constraint random and advised stimulus. • Ensure complete verification coverage through implementation and review of code and functional coverage. • Ensure RTL quality with …

Added Oct 27, 2026

Save job

Nvidia

Senior Chip Design Verification Engineer

Israel, Yokneam +1 location

NVIDIA's Chip Design group is looking for best-in-class Verification Engineers to join our outstanding Silicon Engineering team, developing the industry's best high-speed …

Added Oct 27, 2026

Save job

Nvidia

Senior Chip Design Verification Engineer

Israel, Tel Aviv

NVIDIA is looking for a best-in-class Chip Design Verification Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best …

Added Oct 27, 2026

Save job

Cisco Systems

ASIC Design Engineer Technical Lead

San Jose, California, United States

Pay posted by employer$186,900–$267,700

… methodology. Mentor junior engineers on performing project tasks and problem solving. Collaborate with the verification team to address design bugs and close code coverage. Work closely with physical design team to close design …

Added Oct 27, 2026

Save job

RTX

Senior ASIC/FPGA Design Engineer

McKinney, Texas, United States

The selected candidate will define ASIC/FPGA requirements from system specifications, develop digital architectures, implement RTL designs, and …

Added Oct 27, 2026

Save job

Intel

Senior Core Design Verification Engineer

Malaysia, Penang

The Role and Impact As a CPU Design Verification Engineer, you will play a pivotal role in ensuring the functionality and reliability of cutting-edge CPU …

Added Oct 27, 2026

Save job

Intel

Senior Core Design Verification Engineer

Malaysia, Penang

The Role and Impact As a CPU Design Verification Engineer, you will play a key role in ensuring the reliability and functionality of Intel's next-generation …

Added Oct 27, 2026

Save job

Intel

Sr Deep Learning Verification Engineer

Leixlip, Leinster, Ireland

The Role and Impact As a Sr Deep Learning Hardware Verification Engineer, you will play a pivotal role in shaping the future of AI hardware by validating and optimizing …

Added Oct 27, 2026

Save job

Cisco Systems

ASIC Design Engineer | Exp 8+ Years

Bengaluru, India

… networking company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth …

Added Oct 27, 2026

Save job

Cisco Systems

Senior ASIC RTL Engineer

San Jose, California, United States +1 location

Pay posted by employer$167,700–$245,200

… coding. Prior experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification). Prior experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, …

Added Oct 27, 2026

Save job

Nvidia

Senior Verification Engineer, Memory Subsystem

Bengaluru, Karnataka, India

… and see how you can make a lasting impact on the world! What you’ll be doing: Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies. Expected to …

Added Oct 27, 2026

Save job

RTX

Senior Electrical Engineer - ASIC/FPGA (Onsite)

Cedar Rapids, Iowa, United States

… challenges and to meet the demands of a rapidly evolving global market. We are looking for a Senior FPGA Engineer to be involved in the design, implementation, verification, and integration of a wide variety of …

Added Oct 27, 2026

Save job

Nvidia

ASIC Methodology, Flow and Integration Engineer

Bengaluru, Karnataka, India +1 location

… work. Come join the team and see how you can make a lasting impact on the world. We are now looking for ASIC Flow and Integration Engineer to drive design methodology, automation, and integration for our High Speed …

Added Oct 27, 2026

Save job

Cisco Systems

ASIC DFT Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$155,000–$222,600

View job

Save job

Minimum Qualifications · employer excerpt

Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
Experience with ASIC DFT implementation or validation
Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
Experience with stuck-at and transition fault models

2 more in the full description below.

About this opportunity

Original employer description

This is a hybrid role than can be performed three days per week from our San Jose, CA office.

Meet the Team

Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.

Your Impact

We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product engineering, and test teams to help deliver high-quality test coverage and manufacturability for advanced semiconductor designs. Key responsibilities include:

Support DFT implementation for ASIC / SoC blocks and subsystems
Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic
Run DFT rule checks and debug scan, clock, reset, and test-mode issues
Generate and validate ATPG patterns for stuck-at, transition, and other required fault models
Analyze test coverage, pattern count, compression results, and ATPG reports
Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues
Work with RTL and verification teams to ensure DFT requirements are correctly implemented
Support block-level and full-chip DFT integration activities
Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable
Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting
Support silicon debug, diagnosis analysis, and yield-learning activities as needed
Document DFT implementation results, known issues, waivers, and signoff status

Minimum Qualifications:

Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
Experience with ASIC DFT implementation or validation
Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
Experience with stuck-at and transition fault models
Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures
Scripting experience using Tcl, Python, Perl, or shell

Preferred Qualifications

Experience with hierarchical DFT methodology and block-level signoff
Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows
Experience with MBIST insertion, memory test validation, or BISR flows
Familiarity with gate-level simulation, SDF timing, and pattern validation
Exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug
Experience working on advanced-node ASICs, networking ASICs, or high-performance SoCs
Ability to improve automation, regression checks, and DFT reporting dashboards
Experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation
Scripting experience using Tcl, Python, Perl, or shell
Experience troubleshooting problems related to ASIC DFT and working with cross-functional teams.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$155,000.00 - $256,000.00

Non-Metro New York state & Washington state:

$138,100.00 - $227,900.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Why this result? · Employer labels

Keywords also found in description

Location reference: GeoNames (CC BY 4.0), normalized by Referizz.