116 matching jobs for “Senior DFT Engineer”

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Broadcom

Senior DFT engineer

Yishun New Town, Singapore

Full time
Regular

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for …

Added Oct 9, 2026

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Nvidia

Senior DFT Engineer

US, CA, Santa Clara

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality …

Added Oct 27, 2026

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Nvidia

… and intelligence. Make the choice to join us today. NVIDIA’s DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive …

Added Oct 27, 2026

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Nvidia

Senior DFT Engineer

US, CA, Santa Clara

… Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor …

Added Oct 27, 2026

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Nvidia

Senior DFT Engineer

US, CA, Santa Clara

Added Oct 27, 2026

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Intel

Senior ASIC DFT Engineer

Israel, Haifa

… rigorous thinking, and want real scope and short feedback loops, you'll feel right at home here. This is a senior, hands-on role with broad technical influence. You will own central DFT aspects in our new family of chips …

Added Oct 27, 2026

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Nvidia

Senior DFT Verification Engineer

Israel, Yokneam +1 location

NVIDIA is looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies. As a design …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer - DFT

US, CA, Santa Clara

We are now looking for a Senior ASIC Design Engineer to join our DFT team! NVIDIA has continuously reinvented itself over two decades. Our …

Added Oct 27, 2026

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Nvidia

Senior DFT Engineer - Post Silicon

US, CA, Santa Clara +1 location

As a Senior DFT Engineer - Post-Silicon , you will take pioneering DFT capabilities beyond implementation—connecting silicon …

Added Oct 27, 2026

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Nvidia

Senior DFT Power Methodology Engineer

US, CA, Santa Clara

… testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology …

Added Oct 27, 2026

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Nvidia

Senior DFT - Silicon Validation Engineer

US, CA, Santa Clara

… Our latest innovations support progress in AI. We keep evolving to solve emerging challenges. As a Senior DFT - Silicon Validation Engineer, you will work on ground breaking technologies in DFT to accelerate and …

Added Oct 27, 2026

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Intel

Senior DFT Logic Design Engineer

US, Arizona, Phoenix +2 locations

Pay posted by employer$141,910–$269,100 USD per year

… design packages. Come join us and do something wonderful. The Aerospace, Defense, Government (ADG) - The Senior DFT Logic Design Engineer provides technical support to Intel Foundry Services customers on our PDKs, …

Added Oct 27, 2026

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Nvidia

Senior Circuit Silicon Correlation DFT Engineer

India, Bengaluru

… RAM types, chips and processes and improve correlation in the long run Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM. What we need to see: …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC DFT DV Engineer (Hybrid)

San Jose, California, United States

Pay posted by employer$167,700–$245,200

… for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design Own …

Added Oct 27, 2026

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Cisco Systems

Senior ASIC DFT DV Engineer (Hybrid)

San Jose, California, United States +1 location

Pay posted by employer$167,700–$245,200

Added Oct 27, 2026

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Cisco Systems

ASIC DFT Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$155,000–$222,600

include: Support DFT implementation for ASIC / SoC blocks and subsystems Implement and validate scan insertion, scan …

Added Oct 28, 2026

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Nvidia

Senior DFT Methodology - Data Analytics and Applied AI Engineer

US, CA, Santa Clara

Added Oct 29, 2026

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Boeing

ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior)

USA - Mountain View, CA

In person
Full time
Regular

Pay posted by employer$119,850–$162,150

… tapeout readiness, silicon debug, and cross‑discipline integration with architecture, RTL, verification, DFT, and external backend partners. Position Responsibilities: Design and implement DFT architectures and test …

Added Oct 12, 2026

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Nvidia

Senior JTAG Methodology Engineer

US, CA, Santa Clara

We are now looking for a Senior JTAG Methodology Engineer! As a Senior JTAG Methodology Engineer, you will architect and develop the test …

Added Oct 27, 2026

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Intel

Senior ASIC Verification Engineer

Israel, Haifa

… flow — planning, stimulus and checker development, coverage analysis, debug and more — and we look to our senior verification engineers to help steer that evolution. If you are energized by defining things that have …

Added Oct 27, 2026

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Cisco Systems

ASIC DFT Engineer - Acacia (Hybrid)

San Jose, California, United States

Pay posted by employer$155,000–$222,600

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Minimum Qualifications · employer excerpt

Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
Experience with ASIC DFT implementation or validation
Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
Experience with stuck-at and transition fault models

2 more in the full description below.

About this opportunity

Original employer description

This is a hybrid role than can be performed three days per week from our San Jose, CA office.

Meet the Team

Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.

Your Impact

We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product engineering, and test teams to help deliver high-quality test coverage and manufacturability for advanced semiconductor designs. Key responsibilities include:

Support DFT implementation for ASIC / SoC blocks and subsystems
Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic
Run DFT rule checks and debug scan, clock, reset, and test-mode issues
Generate and validate ATPG patterns for stuck-at, transition, and other required fault models
Analyze test coverage, pattern count, compression results, and ATPG reports
Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues
Work with RTL and verification teams to ensure DFT requirements are correctly implemented
Support block-level and full-chip DFT integration activities
Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable
Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting
Support silicon debug, diagnosis analysis, and yield-learning activities as needed
Document DFT implementation results, known issues, waivers, and signoff status

Minimum Qualifications:

Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
Experience with ASIC DFT implementation or validation
Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent
Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
Experience with stuck-at and transition fault models
Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures
Scripting experience using Tcl, Python, Perl, or shell

Preferred Qualifications

Experience with hierarchical DFT methodology and block-level signoff
Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows
Experience with MBIST insertion, memory test validation, or BISR flows
Familiarity with gate-level simulation, SDF timing, and pattern validation
Exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug
Experience working on advanced-node ASICs, networking ASICs, or high-performance SoCs
Ability to improve automation, regression checks, and DFT reporting dashboards
Experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation
Scripting experience using Tcl, Python, Perl, or shell
Experience troubleshooting problems related to ASIC DFT and working with cross-functional teams.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$155,000.00 - $256,000.00

Non-Metro New York state & Washington state:

$138,100.00 - $227,900.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

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