344 matching jobs for “SoC Design Verification Engineer”

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Intel

Mixed Signal Logic Design Engineer

Malaysia, Penang

Full time
Regular

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or high-speed IPs required to …

Added Oct 27, 2026

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Marvell Technology

Principal, IC Digital Design Engineer

Irvine, California, United States

Full time
Regular

… trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal, Digital IC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group, the team developing the high …

Added Nov 3, 2026

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Nvidia

Senior ASIC Design Engineer - Memory Subsystem

Santa Clara, California, United States

… join the team and see how we can make a lasting impact on the world. NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem Team! What you'll be doing : As a member of our Memory Subsystem …

Added Oct 27, 2026

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Intel

Principal Engineer - Standard Cell Design

Santa Clara, California, United States +4 locations

Full time
Regular

Pay posted by employer$220,920–$311,890 USD per year

… deliver power, performance, and scalability across future nodes and products. We're looking for a Principal Engineer who thrives on solving hard problems, someone who can bring deep circuit expertise and help define the …

Added Oct 27, 2026

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Analog Devices

Senior Engineer, Physical Design Engineering (ASIC)

Somerset, New Jersey, United States +1 location

Pay posted by employer$116,960–$160,820

As a Senior Physical Design Engineer, you will play a key role in the implementation and delivery of complex digital and mixed-signal …

Added Nov 3, 2026

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Cisco Systems

ASIC Design Engineer | Exp 8+ Years

Bengaluru, Karnataka, India

… company in the world! Your Impact Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of …

Added Oct 27, 2026

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Intel

Quantum IC Package Substrate Design Engineer

Hillsboro, Oregon, United States

Full time
Regular

Pay posted by employer$122,440–$172,860 USD per year

… leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for …

Added Oct 27, 2026

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Intel

E-core CPU Layout Design Engineer

Malaysia, Penang +1 location

Full time
Regular

The Role and Impact As an E-Core (Atom) CPU Layout Design Engineer, you will play a pivotal role in shaping the physical layout of Intel's cutting-edge Atom …

Added Oct 27, 2026

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Boeing

Experienced or Senior Digital Design Engineer

USA - Huntsville, AL

In person
Full time
Regular

Pay posted by employer$112,200–$151,800

Design high speed digital circuits and perform signal integrity analysis Focus on electronic systems and …

Added Oct 12, 2026

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Intel

E-core CPU Clock Design Engineer

Malaysia, Penang

Full time
Regular

… CPU products. Whether you're a college graduate eager to launch your career or an experienced engineer ready to solve some of the industry's most complex technical challenges, you'll have the opportunity to …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer – Clocks IP

Santa Clara, California, United States +1 location

The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team …

Added Oct 27, 2026

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Nvidia

Senior ASIC Design Engineer - Agentic AI

Santa Clara, California, United States +2 locations

NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement the world's leading SoC's and GPU's. …

Added Oct 31, 2026

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Northrop Grumman

Principal/ Sr. Principal FPGA Design Engineer

United States-Illinois-Rolling Meadows

Pay posted by employer$119,600–$179,400

… Space Systems today! Our team is chartered with providing the skills, innovative technologies to develop, design, produce and sustain optimized product lines across the sector while providing a decisive advantage to the …

Added Nov 3, 2026

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Intel

Power Delivery Integration and Power Rail Stress Engineer- SoC Power Thermal Performance Validation Engineer (Temporary position)

Guadalajara, Jalisco, Mexico

Full time
Temporary

As a SoC Power Thermal Performance Validation and Optimization Engineer, you will play an essential role in ensuring …

Added Nov 7, 2026

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Analog Devices

Digital Design Manager

China, Beijing, Haidian, Xixiaokou

Technical Leadership Lead block-level and chip-level digital architecture definition, RTL design, and implementation for digital SoCs. Drive key architecture and micro-architecture decisions, balancing …

Added Nov 3, 2026

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Analog Devices

Principal IC Analog / Mixed Signal Design Engineer

Wilmington, Massachusetts, United States

Pay posted by employer$157,080–$227,460

carries both hands-on design ownership and technical leadership of junior and senior engineers. This is a hands-on technical leadership …

Added Nov 3, 2026

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Nvidia

ASIC Design Engineer, BOOT and Power Management

Bengaluru, Karnataka, India +1 location

… work. Come join the team and see how you can make a lasting impact on the world. We are now looking for RTL Design engineers for our BOOT and Power management Subsystem Design deployed in Automotive and Client chips. As …

Added Oct 28, 2026

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Nvidia

ASIC Design Engineer - New College Grad 2026

Santa Clara, California, United States

NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have …

Added Oct 31, 2026

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Nvidia

ASIC Design Engineer - New College Grad 2027

Santa Clara, California, United States

… people in the world and there has never been a more exciting time to join our team! We are seeking an ASIC Design Engineer - New College Graduate to implement the world’s leading SoC's and GPU's. This position offers the …

Added Oct 27, 2026

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Boeing

ASIC / FPGA Digital Design Engineer – (Lead or Senior)

USA - El Segundo, CA +1 location

Full time
Regular

Pay posted by employer$146,200–$197,800

ASIC / FPGA Digital Design Engineer – (Lead or Senior) Company: Boeing Space, Intelligence & Weapons Systems has an exciting …

Added Oct 12, 2026

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Intel

Principal Engineer - Standard Cell Design

Santa Clara, California, United States +4 more

Full time
Regular

Pay posted by employer$220,920–$311,890 USD per year

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Qualifications · employer excerpt

In-depth understanding of MOSFET electrical characteristics, transistor device level physics, layout and variability at advanced technology nodes
Working knowledge of transistor level design of static circuits including state retaining elements such as latches and flops in circuit design, standard cell development, or related domains.
Understanding of std cell circuit design tradeoffs across power, performance, area and Vmin
Experience with standard cell characterization tools and Spice circuit simulations
Experience in identification, design and verification of cells targeted to improve product level PPA

7 more in the full description below.

About this opportunity

Original employer description

Job Details:

Job Description:

Come build what's next in scalable, high-performance silicon.

At Intel, our standard cell libraries sit at the foundation of every product we build. This role is more than designing circuits; it's about shaping how we deliver power, performance, and scalability across future nodes and products.

We're looking for a Principal Engineer who thrives on solving hard problems, someone who can bring deep circuit expertise and help define the direction of library architecture, DTCO, and design methodology. Your work will directly influence how our designs scale across CPU, GPU, and emerging architectures.

Why this role matters
As process nodes become more complex, delivering competitive Power, Performance and Area (PPA) and Vmin requires more than incremental improvements. This role plays a key part in defining the next generation of library design, balancing usability, scalability, and performance while enabling product teams to move faster with confidence.

A day in this role
In this role, you will:

Shape standard cell library strategy, including content definition, cell selection, and ecosystem usability.
Drive circuit innovation for high-performance and low-voltage operation, especially in sequential and clocking circuits.
Lead PPA and Vmin optimization efforts, working through complex tradeoffs across performance, power, and area.
Drive optimization of standard cell libraries on Intel’s leading edge process nodes to meet internal and external foundry customer needs
Directly interface with key Intel foundry customers to understand technology and library gaps and drive co-optimization with Intel foundry technology development teams and EDA partners
Partner with DTCO, product design teams, and EDA partners to align on scalable solutions.
Guide and mentor circuit designers, helping raise the bar on design quality and methodology.
Lead or contribute to working groups, bringing clarity and convergence across diverse stakeholders.
Develop and refine circuit methodology, including naming conventions, modeling approaches, validation frameworks, and best practices.
Analyze silicon and design data to identify outliers, debug issues, and drive improvements.
Partner with process technology teams to define and refine process requirements for standard cell development.
Help define forward-looking directions, including new circuit topologies and design approaches.
Mentor and develop technical leaders within the organization, fostering a culture of growth, collaboration, and excellence

Big challenges you'll take on.

Balancing aggressive PPA and Vmin targets in highly complex and low-voltage regimes.
Simplifying and scaling the library ecosystem across multiple nodes and product lines.
Driving technical alignment across teams with different priorities and constraints.
Making high-impact technical decisions where data may be incomplete or evolving.
Translating complex circuit and system challenges into practical, scalable solutions.

Qualifications

In-depth understanding of MOSFET electrical characteristics, transistor device level physics, layout and variability at advanced technology nodes
Working knowledge of transistor level design of static circuits including state retaining elements such as latches and flops in circuit design, standard cell development, or related domains.
Understanding of std cell circuit design tradeoffs across power, performance, area and Vmin
Experience with standard cell characterization tools and Spice circuit simulations
Experience in identification, design and verification of cells targeted to improve product level PPA
Ability to lead analyze data, identify trend and effectively communicate conclusion
Expertise in low-power, high-performance circuit techniques, including clocking and sequential elements.
Solid understanding of PPA tradeoffs, Vmin behavior, and variation impacts.
Ability and willingness to proactively support development of junior engineers
Collaborative mindset and great team player
Excellent oral and written communication skills
Strong problem-solving skills in ambiguous, complex environments.

Qualifications:

Minimum Qualifications

Ph.D. or Master's degree
With 10+ years of industry experience with foundation IP design, design-technology co-optimization & advanced semiconductor technology.

Preferred Qualifications

Good track record of technical leadership and delivery
Experience in designing around local layout effect & technical leadership and/or management
Some understanding or experience of block-level design tool for feedback to optimize standard cell library content and/or design
Background in compact modeling, characterization, or EDA tool interaction.
Experience working across CPU, GPU, or SoC design teams.
Publications, patents, or recognized technical contributions.
Experience leading working groups or driving cross-org technical alignment.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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Keywords also found in description

Full time
Regular
Silicon Hardware Engineering

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