173 matching jobs for “CPU Physical Design Engineer”

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Nvidia

Senior System Integration and Validation Engineer

Santa Clara, California, United States

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our …

Added Oct 27, 2026

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Senior Windows Operating System Engineer

Taipei, Taiwan, Taiwan

Full time
Reg Employee

… Strong understanding of Microsoft Windows architecture (x86 & ARM), component, driver and firmware design and requirements. Familiarity with hardware platforms from Intel, AMD, Qualcomm, and Nvidia. Strong …

Added Oct 22, 2026

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Intel

Cloud and AI System Engineer

PRC, Shanghai

The Role and Impact We are seeking a motivated Cloud Systems and Solutions Engineer to design and develop innovative cloud and AI systems that integrate software, firmware, board, and …

Added Oct 27, 2026

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Visa

Software Development Engineer- Product Reliability Engineering

Austin, Texas, United States

Hybrid

… pay- Visa infrastructure makes it happen in milliseconds, across 200+ countries. As a Software Development Engineer on the Product Reliability Engineering (PRE) team, you won’t just watch those systems run- you’ll be one of …

Added Oct 31, 2026

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Lowe's

Lead AI Engineer - AI Platform

Lowe's Charlotte Technology Hub 3505

… learning (ML) models, including deep learning (DL) frameworks and large language models (LLMs). The Lead AI Engineer will be responsible for leading the advancement of model performance, implementing essential tools and …

Added Oct 27, 2026

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Cisco Systems

Splunk Staff Software Engineer - Performance Optimization & Innovation (PerfOpt)

Kraków, Lesser Poland, Poland

… through deep performance work, and sets Splunk's long-term performance standards through guidelines and design. We work where performance is won or lost: search and indexing hot paths, cache and bloomfilter efficiency, …

Added Oct 27, 2026

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Nvidia

Senior High-Speed IO Validation Engineer

Santa Clara, California, United States

We are now looking for a Senior High-Speed IO (HSIO) Validation Engineer to join our hardware product team! This is an outstanding opportunity to work with next-generation GPU, CPU …

Added Oct 31, 2026

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Visa

Software Development Engineer- Product Reliability Engineering

Denver, Colorado, United States

Added Oct 31, 2026

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Palo Alto Networks

Principal Engineer Software - NGFW (NetSec) - Bangalore

Office - India - Bangalore Bagmane Tech Park

… everyday lives that are only enabled by a secure digital environment. Job Summary We are hiring a Principal Engineer Software to own the health, reliability, and release engineering of PA-VM, our virtualized next-generation …

Added Oct 27, 2026

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Intel

Hardware Platform Applications Engineer - Military & Aerospace

Phoenix, Arizona, United States +3 locations

Pay posted by employer$122,440–$232,190 USD per year

… be joining the Intel Government Technologies Customer Engineering team as a Hardware Platform Applications Engineer (PAE). This is an exciting organization with a revamped roadmap looking to expand Intel's footprint into …

Added Oct 27, 2026

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AT&T

Lead Embedded Firmware Engineer – Residential Gateways (prplOS & Wireless)

Hyderabad, India +1 location

Remote
Full time
Regular

Technical Leadership & Architecture: Lead the architectural design of resilient, hardware-agnostic gateway firmware, mentoring engineering teams and establishing embedded …

Added Oct 15, 2026

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Cisco Systems

Splunk Senior Staff Software Engineer - Performance Optimization & Innovation (PerfOpt)

Kraków, Lesser Poland, Poland

Added Oct 27, 2026

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Nvidia

Senior Product Quality Engineer, Board – Automotive

Santa Clara, California, United States

… identifying root-cause of customer reported issues – Perform PCB-level debugging to isolate faults for physical FA. Investigate NVIDIA product failures and determine solutions through lab experimentation and …

Added Oct 27, 2026

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Cisco Systems

Software Engineer-Network programming, SDK, C/C++, P4

Bengaluru, Karnataka, India

• Design, develop, and enhance software for Cisco's Nexus data center switching platforms. • Lead the implementation …

Added Oct 27, 2026

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Intel

AI Silicon Performance Modeling and Analysis Engineer

Santa Clara, California, United States

Pay posted by employer$141,910–$232,190 USD per year

… team is responsible for developing and maintaining performance models that enable architecture exploration, design evaluation, scalability analysis, and performance projection for next-generation AI silicon products. These …

Added Nov 1, 2026

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Cisco Systems

UI Desktop Engineer Hybird, North Carolina Hybrid

RTP, North Carolina, US

Pay posted by employer$115,800–$163,200

Design, build, and maintain the Circuit Desktop application for macOS and Windows using Electron (or Tauri) with …

Added Oct 27, 2026

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Cisco Systems

UI Desktop macOS and IOS Engineer Hybird

RTP, North Carolina, US +1 location

Pay posted by employer$115,800–$163,200

Design, build, and maintain the Circuit Desktop application for macOS and Windows using Electron (or Tauri) with …

Added Oct 27, 2026

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Intel

GPU Driver and Graphics Performance Engineer

Hillsboro, Oregon, United States +2 locations

Pay posted by employer$111,030–$181,940 USD per year

… and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something …

Added Oct 28, 2026

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Palo Alto Networks

Principal Software Engineer - ADEM Agent (Client/Endpoint Focus)

Santa Clara, California, United States

… of innovation at Palo Alto Networks. We don't just follow industry trends; we create them. As a Principal Engineer focused on the Agent, you will be at the center of this mission, tackling "impossible" problems in scale, …

Added Oct 27, 2026

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KLA

High Performance Compute (HPC) Software Engineer – HPC SW Systems

Ann Arbor, Michigan, United States

Full time
Regular

Pay posted by employer$105,900–$155,300 per year

… delivering high-impact work across your area of expertise. Key Responsibilities HPC Software Engineering · Design, develop, and optimize HPC software running on large-scale Linux clusters, including distributed and …

Added Oct 15, 2026

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Nvidia

Senior System Integration and Validation Engineer

Santa Clara, California, United States

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About this opportunity

Original employer description

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first.

We are hiring a Senior Engineer to lead system validation, debug, and cross-functional alignment on one of our most consequential silicon programs. Your work will sit on the critical path of every flagship build, and the judgment you bring to ambiguous, multi-team failures is the difference between shipping on milestone and slipping! The two hardest, highest-leverage problems in this seat:

Find critical silicon and platform issues before they reach the customer — by shifting validation coverage left with system stress, PVT, and feature-interaction tests that catch escapes before software hardens. Your work shows up in DPPM, escape rate, and ramp confidence.
Build AI-enabled validation as a real capability, not a demo — by deploying debug, triage, root-cause hypothesis generation, and regression workflows with the evals and guardrails that make them trustworthy enough to gate production decisions.

What you’ll be doing:

Own end-to-end system validation of NVIDIA GPU, SoC, and platform programs — feature checks, PVT stress, system-stress campaigns at scale, and multi-unit fleet testing.
Lead debug of the hardest cross-stack issues — logic, signal integrity, power delivery, firmware, and software interaction — and drive them to root cause with reusable workarounds and productized fixes.
Develop test plans, scripts, and automation for next-generation chips ahead of physical builds, translating architecture, boot flows, high-speed I/O, and power and thermal dependencies into executable coverage.
Design and deploy AI-enabled debug and validation workflows used by the team — with explicit guardrails (evals, regression validation, false-positive handling) and measurable impact on cycle time, debug velocity, or escape rate.
Translate complex silicon and system risk into decision-ready options for technical and executive audiences — without padding or hand-waving.
Partner with globally distributed teams across silicon design, DFT, firmware, software, manufacturing, and platform engineering — including counterpart engineers in India and other major hubs.
Lead crisis-mode debug task forces when a program is stuck, and convert the learnings into reusable methodology for adjacent programs.

What we need to see:

BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience), plus 8+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.
Hands-on debug depth across silicon, board, and software boundaries — logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior — with strong EE fundamentals across SI/PI, power delivery, and thermal, and a working understanding of GPU, CPU, or SoC architecture across PC, Datacenter, or Automotive.
At least one specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a track record of leading a project team end-to-end through a real crisis with decision points you owned.
Demonstrated AI-driven validation workflow you built or scaled, not just used — with adoption beyond yourself and measurable impact on debug velocity, coverage, or escape rate. You can describe the guardrails you put in place and where AI is dangerous in your workflow.

Ways to stand out from the crowd:

A history of building reusable validation methodology, debug playbooks, or test frameworks that were adopted by other programs or teams — backed by patents, conference papers, invited talks, or recognized contributions.
Hands-on subsystem depth in HBM, SerDes or high-speed I/O, power and thermal, or advanced packaging — failure modes, debug instrumentation, and the tradeoffs that show up in production.
Experience partnering deeply with a counterpart team in India or another major engineering hub — examples of shared culture, shared metrics, and shared on-call across geographies.
AI work that goes beyond personal-copilot use — agentic workflows, RAG-grounded debug assistants, regression bucketing, or automated triage deployed at team scope with adoption metrics.

NVIDIA is the world leader in accelerated computing, and our work powers AI, gaming, robotics, autonomous systems, and scientific discovery. We invest in our people with competitive benefits, flexible time off, and continuous learning, and we build a team where everyone can do their best work. Come help us build chips that change what is possible!

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 27, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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